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2009-11-07nv50: enable all 32 threads of a warpChristoph Bumiller
This should be the default setting. See also 7d967b9b7c08aea2a471c5bf6aced8bfafdae874.
2009-11-06i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt
No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size.
2009-11-06i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
2009-11-06i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
This should fix issues with antialiased lines in GLSL.
2009-11-06i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst.
2009-11-06i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt
2009-11-06i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt
2009-11-06i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt
This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
2009-11-06i965: Collect GLSL src/dst regs up in generic code.Eric Anholt
This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced.
2009-11-06st/xorg: implement batching for the composite opZack Rusin
something is broken so disabled for now
2009-11-06st/xorg: batch solid fill requestsZack Rusin
instead of lots of very small transfers, one larger is a lot better for performance
2009-11-06st/xorg: start accumulating vertices in a common bufferZack Rusin
2009-11-06st/xorg: use quads instead of triangle fansZack Rusin
easier to split, accumulate and batch those
2009-11-06st/xorg: make the buffer size globalZack Rusin
2009-11-06mesa: Reduce the source channels considered in optimization passes.Eric Anholt
Depending on the writemask or the opcode, we can often trim the source channels considered used for dead code elimination. This saves actual instructions on 965 in the non-GLSL path for glean glsl1, and cleans up the writemasks of programs even further.
2009-11-06mesa: Fix remove_instructions to successfully remove when removeFlags[0].Eric Anholt
This fixes the dead code elimination to work on the particular code mentioned in the previous commit.
2009-11-06mesa: Add an optimization path to remove use of pointless MOVs.Eric Anholt
GLSL code such as: vec4 result = {0, 1, 0, 0}; gl_FragColor = result; emits code like: 0: MOV TEMP[0], CONST[0]; 1: MOV OUTPUT[1], TEMP[0]; and this replaces it with: 0: MOV TEMP[0], CONST[0]; 1: MOV OUTPUT[1], CONST[0]; Even when the dead code eliminator fails to clean up a now-useless MOV instruction (since it doesn't do live/dead ranges), this should at reduce dependencies.
2009-11-06mesa: Fix up the remove_dead_code pass to operate on a channel basis.Eric Anholt
This cleans up a bunch of instructions in GLSL programs to have limited writemasks, which would translate to wins in shaders that hit the i965 brw_wm_glsl.c path by depending less on in-driver optimizations. It will also help hit other optimization passes I'm looking at.
2009-11-06intel: better front color buffer test in intelClear()Brian Paul
2009-11-06i965: Always pass the size argument to brw_cache_data.Eric Anholt
This keeps the individual state files from having to export their structures for brw_state_cache initialization.
2009-11-06intel: Finish removing the fallback code for bug #16697.Eric Anholt
I fixed it properly as of 7216679c1998b49ff5b08e6b43f8d5779415bf54.
2009-11-06intel: Don't validate in a texture image used as a render target.Eric Anholt
Otherwise, we could lose track of rendering to that image, which could easily happen during mipmap generation.
2009-11-06mesa: Attempt to pair up Driver.RenderTexture and FinishRenderTexture()Eric Anholt
This is probably not 100% complete (bind vs unbind may still not pair up exactly), but it should help out drivers which are relying on FinishRenderTexture to be called when we're done rendering to a particular texture level, not just when we're done rendering to the object at all. This is the case for the one consumer of FinishRenderTexture() so far: the gallium state tracker. Noticed when trying to make use of FRT() in the intel driver.
2009-11-06intel: Clean up some extra struct indirection in finalize.Eric Anholt
2009-11-06intel: Use _mesa_get_current_tex_object() to clean up TFP path.Eric Anholt
2009-11-06intel: Remove duplicated arguments from intel_miptree_match_image().Eric Anholt
2009-11-06i965: Remove an XXX comment for testing some code that seems to work.Eric Anholt
2009-11-06intel: Remove obsolete comment about GEM in the spans code.Eric Anholt
2009-11-06intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.Eric Anholt
This should do all the things that MI_FLUSH did, but it can be pipelined so that further rendering isn't blocked on the flush completion unless necessary.
2009-11-06Make a convenient int for what chipset generation we're on.Eric Anholt
gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc", and compares on generation are often easier than stringing together a bunch of chipset checks.
2009-11-06Merge branch 'mesa_7_6_branch'Ian Romanick
This should fix the memory leaks in the assembly parser without the regressions. The conflicts in program_lexer.l were related to changes in returning strings between the branches (always return IDENTIFIER vs. returing either IDENTIFIER or USED_IDENTIFIER). The conflicts in program_parse.y were related to two changes in master One change prints a variable name in an error message. The other change adds outputVarSize to the OUTPUT_statement rule. The cause the position of the IDENTIFIER to change from $2 to $3. Conflicts: src/mesa/shader/lex.yy.c src/mesa/shader/program_lexer.l src/mesa/shader/program_parse.tab.c src/mesa/shader/program_parse.y
2009-11-06ARB prog parser: Regenerate parser from previous commits.Ian Romanick
2009-11-06ARB prog parser: Release old program string in ↵Ian Romanick
_mesa_parse_arb_{fragment,vertex}_program The program structure passed to _mesa_parse_arb_program is just a place holder. The stings that actually need to be released are only known to the functions calling _mesa_parse_arb_program, so they should be freed there.
2009-11-06ARB prog parser: Release strings returned from the lexer that don't need to ↵Ian Romanick
be kept
2009-11-06Revert "ARB prog parser: Fix epic memory leak in lexer / parser interface"Ian Romanick
This reverts commit 93dae6761bc90bbd43b450d2673620ec189b2c7a. This change was completely broken when the parser uses multiple strings in a single production. It would be nice if bug fixes could initially land somewhere other than the stable branch.
2009-11-06llvmpipe: Fix build with llvm 2.6.José Fonseca
Fixes bug 24949.
2009-11-06intel: call intel_check_front_buffer_rendering() in intelClear()Brian Paul
fixes bug 24953.
2009-11-06mesa: Export S3_s3tc as well.José Fonseca
Used in Quake3.
2009-11-06mesa: Translate MAP_UNSYNCHRONIZED_BIT.José Fonseca
2009-11-06gallium: Add UNSYNCHRONIZED cpu access flag. Document others.José Fonseca
2009-11-06st/xorg: unify vertex buffer handlingZack Rusin
first step on our way to batching
2009-11-05xmesa: pass pixmap to clip_for_xgetimage()Brian Paul
The code was assuming ctx->DrawBuffer == ctx->ReadBuffer. Passing the pixmap is simpler and better. Fixes a potential segfault.
2009-11-05mesa: fix infinite loop bug in _mesa_drawbuffers()Brian Paul
Fixes bug 24946. This regression came from 8df699b3bb1aa05b633f05b121d09d812c86a22d.
2009-11-05softpipe: Implement PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE for destination.José Fonseca
It is a valid and tested combination on D3D9.
2009-11-05g3dvl: remove a debug lineCooper Yuan
2009-11-05g3dvl: add scissor settingCooper Yuan