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Build was broken by commit 9666529b5a5be1fcde82caadc2fe2efa5ea81e49
I'm not certain that this is entirely the correct fix since the demo
from bug #23774 seemed to work before the commit that broke the build.
Signed-off-by: Robert Noland <rnoland@2hip.net>
Signed-off-by: Brian Paul <brianp@vmware.com>
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The main issue is we didn't always have a gallium texture object with
enough space to store the to-be-generated mipmap levels. When that's
the case, allocate a new gallium texture and use st_texure_finalize()
to copy images from the old texture to the new one.
We also had the baseLevel parameter to st_render_mipmap() wrong.
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Don't compute the st_texture_object::lastLevel field based on the texture
filters. Use the _MaxLevel value that core Mesa computes for us.
When called from the GenerateMipmap path, we'll use the lastLevel field
as-is.
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Avoids an unnecessary fallback.
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Bug #23760 (crashes in wine)
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This fixes the clears in openarena with the new metaops clear code, and
the new piglit vbo-subdata-sync test.
Bug #23857.
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Its flagging of extra state that's already flagged by the vtbl new_batch
when appropriate was confusing my tracking down of the OA clear bug.
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This is similar to what r300 does inside the driver, but I've added it as
a generic option since it seems most hardware will want it.
Fixes piglit nv-init-zero-reg.vpfp and nv-init-zero-addr.vpfp.
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This helps let drivers treat NV_vp like ARB_vp.
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At the time of the enable there may not be a Z buffer, but one
may be attached to the FBO later.
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If the currently bound FBO isn't yet validated it's possible for
rgbMode to be zero so we'll lose the texture enable.
This could fix some FBO rendering glitches, but I don't know of
any specific instances.
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If there happened to be a bound VBO when intel_generate_mipmap() was
called we blew up because of a bad vertex array pointer.
Fixes regnumonline, bug 23859.
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Otherwise some apps will emit tons of warnings.
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Radeon generic scissors code had problem that some of code was using exclusive
and some inclusive bottom right corner. Only r600 driver is using exclusive
coordinate so changed generic code to pass inclusive coordinate and r600 driver
changes BR coordinate to be exclusive.
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This fixes the glean/glsl1 "texture2D(), with bias" test when using SSE.
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seems to work here ...
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128 gprs, 256 reg-based consts
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- max texture size is 8k, but mesa doesn't support
that at the moment.
- attempt to set shader limits to what the hw actually
supports
- clean up some old r300 cruft
- no need to explicitly disable irqs. This is fixed
in the drm now.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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- MUL_LIT is ALU.Trans instruction
- some Trans instructions can take 3 arguments
- don't clobber dst.x, use dst.z as temp, it'll get written correct
value in last insn
- respect source swizzles
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registers takes radius
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1D tile span support for depth/stencil/color/textures
Z and stencil buffers are always tiled, so this fixes
sw access to Z and stencil buffers. color and textures
are currently linear, but this adds span support when we
implement 1D tiling.
This fixes the text in progs/demos/engine and progs/tests/z*
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Noticed by rnoland on IRC.
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with some minor updates from Richard.
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noticed by taiu on IRC.
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We use t->bo for dri1 since r600 uses CS for dri1.
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if we have a BO here it means TFP and we should have set it
up already.
tested by b0le on #radeon
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Fixes #22741
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Mostly fixes progs/demos/lodbias when MESA_TEX_PROG=1. But the LOD still
seems off by -1 or so.
May be an issue with the params passed to _swrast_compute_lambda()
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