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Move drv->API.Terminate call to eglTerminate. Remove
_eglReleaseDisplayResource as drivers are doing it.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
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Move some fields of _EGLDriver to _EGLDisplay. It also becomes
unnecessary to pass _EGLDisplay to drivers when _eglMain is called.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
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Driver is chosen and preloaded when eglGetDisplay is called. Later when
eglInitialize is called, the same driver is matched to initialize the
display. Also, add new, but unused, hooks to EGLDriver to allow a
driver to probe a display or unload itself.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
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The motivation is so that drivers do not need to look up and check for
bad display, context, and etc. It also becomes unnecessary for drivers
to call the link functions.
This commit makes eglapi.[ch] do the lookup and check. As a result, the
driver API is overhauled, and almost all sources and drivers need
update. The updates are mainly find and replace with human brains.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
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Move to common code base so radeon/r200 can add support for this.
Make OQ start a state emitted like all normal state, and make no-tcl
flushing work in proper places.
Really need a generic post emit space reservation mechanism like max_state
so we can reserve some space for the emit
this code passes demos/arbocclude, piglit occlusion query and
glean occlusion query with TCL and NO-TCL on my rv530.
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This fixes invalid values for CondStackTop, LoopStackTop, etc.
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make sure the number of indices is valid for the
requested prim type. glxgears sends invalid
quad strips with only 2 indices for example.
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This stuff was a vestige of the r600 bring up and
now mostly serves to periodically break the build.
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- This fixes neverball corruption.
- I'm unsure about what we're actually flushing here.
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The value is an enum, not a bitmask.
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Split vbo rendering when the number of elements requested
by drawarrays is bigger than 65536.
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It's the front stencil methods that have contiguous offsets,
not the back ones.
Unfortunately the names in the header still have FRONT/BACK
reversed, so I'm using hex values until it gets updated.
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- We cannot assume all state objects are present when the pipe context changes.
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The TEX instruction is passed the first index of a contiguous
range of 4 TEMP registers that contain coordinates / LOD and,
after execution, the texel values.
It seems the first index is required to be a multiple of 4 on
some (older ?) cards.
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Supported only on HW with TCL block and with proper radeon drm.
Required minimum radeon drm version is 1.30 or KMS.
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TODO:
- use proper interface for checking if bo is idle when it's available
- disable ZTOP only when needed
- make it work under KMS
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Hopefully this gets the ordering correct so the space checks don't fail.
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Based on Maciej's code, just fixed up the alignments for INDX_BUFFER
ut2004 runs AS-Convoy
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if stride is 0 we cannot use count as max index for bounds checking,
since the hardware will simply return 0 as data for indices failing
bounds check. If stride is 0 any index should be valid hence simply
disable bounds checking in this case.
This fixes bugs introduced with e643bc5fc7afb563028f5a089ca5e38172af41a8.
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Conflicts:
src/mesa/drivers/dri/r300/r300_draw.c
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This prevents the driver from discarding a buffer when the whole buffer
is mapped for writing, but only a portion is effectively written.
This is a temporary fix, because WRITE shouldn't imply DISCARD.
The full fix implies using PIPE_BUFFER_USAGE_DISCARD, throughout
the code, and will go only into master.
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