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2010-09-20r600g: move chip class to radeon common structureJerome Glisse
So texture code can be shared btw new state design & old one. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-20glsl: Fix broken handling of ir_binop_equal and ir_binop_nequal.Kenneth Graunke
When ir_binop_all_equal and ir_binop_any_nequal were introduced, the meaning of these two opcodes changed to return vectors rather than a single scalar, but the constant expression handling code was incorrectly written and only worked for scalars. As a result, only the first component of the returned vector would be properly initialized.
2010-09-20glsl: Add comments to clarify the types of comparison binops.Kenneth Graunke
2010-09-20docs: mark as obsolete, remove dead linksBrian Paul
2010-09-20docs: remove old broken linkBrian Paul
2010-09-20glsl2: silence compiler warnings in printf() callsBrian Paul
Such as: "ir_validate.cpp:143: warning: format ‘%p’ expects type ‘void*’, but argument 2 has type ‘ir_variable*’"
2010-09-20mesa: don't call valid_texture_object() in non-debug buildsBrian Paul
This reverts commit c32bac57ed445e48856d74113364287ed6e5cdd4 and silences the warning differently. The _mesa_reference_texobj() function is called quite a bit and we don't want to call valid_texture_object() all the time in non- debug builds.
2010-09-20glsl: Add doxygen commentsIan Romanick
2010-09-20i915g: Link with wrapper sw winsys with sconsJakob Bornecrantz
2010-09-20svga: Integer constant register file has a separate namespace.Michal Krol
Count int and float constants independently. Since there are only few i# constants available and hundreds of c# constants, it would be too easy to end up with an i# declaration out of its range.
2010-09-20svga: Fix relative addressing translation for pixel shaders.Michal Krol
Pixel shaders do not have address registers a#, only one loop register aL. Our only hope is to assume the address register is in fact a loop counter and replace it with aL. Do not translate ARL instruction for pixel shaders -- MOVA instruction is only valid for vertex saders. Make it more explicit relative addressing of inputs is only valid for pixel shaders and constants for vertex shaders.
2010-09-19r600g: Cleanup viewport floats.Corbin Simpson
2010-09-19r600g: Clean up PS setup.Corbin Simpson
I didn't do r600d according to the docs; I split EXPORT_MODE to be a bit more useful and obvious. Hope this is okay.
2010-09-20r600g: only flush for the correct colorbuffer, not all of them.Dave Airlie
2010-09-20r600g: add missing BC_INST wrapper for evergreenDave Airlie
2010-09-20r600g: fixup r700 CB_SHADER_CONTROL register.Dave Airlie
r600c emits this with a mask of each written output.
2010-09-20r600g: fix r700 cube map sizing.Dave Airlie
this fixes fbo-cubemap on r700.
2010-09-20r600g: add color/texture support for more depth formats.Dave Airlie
2010-09-20r600g: add z16 to color setupDave Airlie
2010-09-20r600g: fix tiling support for ddx supplied buffersDave Airlie
needed to emit some more relocs to the kernel.
2010-09-19r600g: "tmp" is such a bad name for a texture.Corbin Simpson
2010-09-19r600g: Fix false and true.Corbin Simpson
2010-09-19r600g: Clean up some indentation and |= vs. | usage.Corbin Simpson
2010-09-19r600g: Deobfuscate and comment a few more functions in r600_hw_states.Corbin Simpson
2010-09-19r600g: Trivially deobfuscate r600_hw_states.Corbin Simpson
2010-09-19r600g: Use align() instead of handrolled code.Corbin Simpson
2010-09-20r600g: drop debugging that snuck inDave Airlie
2010-09-20r600g: clean up valgrind issues on maxtargets test.Dave Airlie
2010-09-20r600g: fix fbo-drawbuffers-maxtargetsDave Airlie
we were leaking buffers since the flush code was added, it wasn't dropping references. move setting up flush to the set_framebuffer_state. clean up the flush state object. make more space in the BOs array for flushing.
2010-09-20r600g: send correct surface base update for multi-cbufsDave Airlie
2010-09-20r600g: modify index buffers for sizes the hw can't deal with.Dave Airlie
this just uses the common code from r300g now in util to do translations on r600g.
2010-09-20util/r300g: split the r300 index buffer modifier functions out to utilDave Airlie
These can be used by other drivers, like r600g. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-09-20r600g: fix exports_ps to export a number not a mask.Henri Verbeet
2010-09-20scons: Link against talloc in the Gallium DRI driversJakob Bornecrantz
2010-09-20rbug: Add function to get opcode name stringJakob Bornecrantz
2010-09-20rbug: Cast opcode to corrent int sizeJakob Bornecrantz
2010-09-19Revert "r600g: Flush upload buffers before draws instead of before flushes."Henri Verbeet
This reverts commit a1d9a58b825825723f1c5f7705f2ed3ef834038a. Flushing the upload buffers on draw is wrong, uploads aren't supposed to cause flushes in the first place. The real issue was radeon_bo_pb_map_internal() not respecting PB_USAGE_UNSYNCHRONIZED.
2010-09-19r600g: Respect PB_USAGE_UNSYNCHRONIZED in radeon_bo_pb_map_internal().Henri Verbeet
2010-09-19gallium/docs: Fixed a typo in the SCS opcode description.Tilman Sauerbeck
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
2010-09-19auxiliary: fix depth-only and stencil-only clearsLuca Barbieri
Depth-only and stencil-only clears should mask out depth/stencil from the output, mask out stencil/input from input, and OR or ADD them together. However, due to a typo they were being ANDed, resulting in zeroing the buffer.
2010-09-19r600g: Buffer object maps imply a wait.Henri Verbeet
Unless e.g. PB_USAGE_DONTBLOCK or PB_USAGE_UNSYNCHRONIZED would be specified.
2010-09-19r600g: Remove a redundant flush in r600_texture_transfer_map().Henri Verbeet
radeon_ws_bo_map() will already take care of that if needed.
2010-09-19r600g: Check for other references before checking for existing mappings in ↵Henri Verbeet
radeon_bo_pb_map_internal(). Having a non-NULL data pointer doesn't imply it's safe to reuse that mapping, it may have been unmapped but not flushed yet.
2010-09-19r600g: Flush upload buffers before draws instead of before flushes.Henri Verbeet
If a upload buffer is used by a previous draw that's still in the CS, accessing it would need a context flush. However, doing a context flush when mapping the upload buffer would then flush/destroy the same buffer we're trying to map there. Flushing the upload buffers before a draw avoids both the CS flush and the upload buffer going away while it's being used. Note that u_upload_data() could e.g. use a pool of buffers instead of allocating new ones all the time if that turns out to be a significant issue.
2010-09-19egl: Enable drm platform by default.Chia-I Wu
This enables EGL_MESA_drm_display for st/egl in the default setup.
2010-09-19st/egl: s/kms/drm/ on the drm backend.Chia-I Wu
s/kms/drm/, s/kdpy/drmdpy/, and so forth.
2010-09-19st/egl: Rename kms backend to drm.Chia-I Wu
The main use of the backend is to support EGL_MESA_drm_display. drm should be a better name.
2010-09-19st/egl: Split modeset code support to modeset.c.Chia-I Wu
The modeset code supports now obsolete EGL_MESA_screen_surface. Move it to a file of its own.
2010-09-19r600g: only emit uses waterfall on r6xx hw.Dave Airlie
2010-09-19r600g; add uses waterfall to asm cf for r6xx.Dave Airlie
On r6xx if an MOVA instruction is emitted we should set this bit.
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