Age | Commit message (Collapse) | Author |
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- We cannot assume all state objects are present when the pipe context changes.
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The TEX instruction is passed the first index of a contiguous
range of 4 TEMP registers that contain coordinates / LOD and,
after execution, the texel values.
It seems the first index is required to be a multiple of 4 on
some (older ?) cards.
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Hopefully this gets the ordering correct so the space checks don't fail.
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Based on Maciej's code, just fixed up the alignments for INDX_BUFFER
ut2004 runs AS-Convoy
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if stride is 0 we cannot use count as max index for bounds checking,
since the hardware will simply return 0 as data for indices failing
bounds check. If stride is 0 any index should be valid hence simply
disable bounds checking in this case.
This fixes bugs introduced with e643bc5fc7afb563028f5a089ca5e38172af41a8.
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Conflicts:
src/mesa/drivers/dri/r300/r300_draw.c
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This info is essential to using/debugging a shader outside of its normal
application.
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We want the post-link program at this points.
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Tests if the current shader/program is valid and that the framebuffer is
complete. To be called by glBegin, glDrawArrays, etc.
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(cherry picked from master, commit 9a8781bd24730374e14568f67f7db8a9cc444bb4)
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This adds two --with configure options for setting defines for
MAX_WIDTH and MAX_HEIGHT. It's conceivably just as easy to define
these in CFLAGS manually, but this way users don't need to know
about internal Mesa details.
Patch updated by BrianP to set DEFINES, not CFLAGS.
(cherry picked from master, commit 7085dce750f478312a47f474330d63cc900a8448)
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Conditionalize MAX_WIDTH / MAX_HEIGHT defines so that users can
set them via CFLAGS.
(cherry picked from master, commit 66bc17e80e22d8f205cc02171b1c266feab6631f)
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Now there is just a single, struct __GLXcontextRec, which is the
GLXContext typedef has already been defined as a pointer to. I
believe this is the intended usage, that GLX implementations should
define that struct as they require.
Merge the two previous structs into one and get rid of the
no-longer-necessary type casts and sub-classing.
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Put the assertions after the error checks.
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The hardware expects a texture's tile mode to change with
the mipmap level.
Also, only multiply by block size once to obtain size.
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Since we don't turn off scissors, we need to update the
stateobj when the framebuffer size changes.
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Now that we know how to make the hardware have y-coordinate origin
top, we can get rid of all the inversion introduced earlier.
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Revert to previous behaviour of dropping to big render operations.
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Copy elements directly to DMA bo to get rid of one memcpy, and prepare for using VBOs for index buffer.
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This doesn't remove software TCL path - so RS480 and RS690 work as before.
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This adds two --with configure options for setting defines for
MAX_WIDTH and MAX_HEIGHT. It's conceivably just as easy to define
these in CFLAGS manually, but this way users don't need to know
about internal Mesa details.
Patch updated by BrianP to set DEFINES, not CFLAGS.
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Conditionalize MAX_WIDTH / MAX_HEIGHT defines so that users can
set them via CFLAGS.
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Using drm_i915_sarea_t instead of struct drm_i915_sarea seems to be
a common standard now, therefore fix it also in intel_context
structure. Additionally this silences a compiler warning:
intel_swapbuffers.c: In function `intelFixupVblank':
intel_swapbuffers.c:48: warning: initialization from incompatible pointer type
Signed-off-by: Tobias Doerffel <tobias.doerffel@gmail.com>
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Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
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Reported by adamk on #radeon
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