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It's hard to form PPC vector immediates so load them from an array.
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gears runs with it now (3x faster FPS than before).
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Plus, add ppc_reserve_register() func.
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Works, but dead code lingering, debug code present, etc.
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Based on the TGSIto SSE2 code generator.
Incomplete and lots of SSE stuff still hanging around but the basic dozen
or so TGSI opcodes are functioning.
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Fixes regressions seen in progs/samples/prim.c, progs/demos/ray.c
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(cherry picked from commit 23cc303994eb630c56b1224dfdac51dcea41ed03)
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immediate field
This type of checking should be expanded to cover more instructions...
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These are the defects found and fixed so far. Several more have
been observed; I'm working on them.
- Fixed an error in spe_load_uint() that caused incorrect values to be
loaded if the given unsigned value had the low 18 bits as 0,
and that caused inefficient code to be emitted if the given value
had the high 14 bits as 0.
- Fixed a problem in stencil code generation where optional registers
weren't tracked correctly.
- Fixed a problem that the stencil function NEVER was acting as ALWAYS.
- Fixed several problems that could occur if stenciling were enabled but
depth was disabled.
- Fixed a problem with two-sided stencil writemask handling that could
cause a stencil writemask to not be applied.
- Fixed several state permutations that were incorrectly flagged as
not requiring stencil values to be calculated.
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Conflicts:
src/gallium/auxiliary/gallivm/instructionssoa.cpp
src/gallium/auxiliary/gallivm/soabuiltins.c
src/gallium/auxiliary/rtasm/rtasm_x86sse.c
src/gallium/auxiliary/rtasm/rtasm_x86sse.h
src/mesa/main/texenvprogram.c
src/mesa/shader/arbprogparse.c
src/mesa/shader/prog_statevars.c
src/mesa/state_tracker/st_draw.c
src/mesa/vbo/vbo_exec_draw.c
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Used for SIN, COS, EXP2, LOG2, POW instructions. TEX next.
Fixed some bugs in MIN, MAX, DP3, DP4, DPH instructions.
In rtasm code:
Special-case spe_lqd(), spe_stqd() functions so they take byte offsets but
low-order 4 bits are shifted out. This makes things consistant with SPU
assembly language conventions.
Added spe_get_registers_used() function.
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Don't use register qualifier. Doxygen-ize comments. Remove 'extern'.
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git+ssh://marcheu@git.freedesktop.org/git/mesa/mesa into gallium-0.2
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Notably, gears doesn't.
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Besides meaning x86 and x86-64 architecture, it also depends on SSE2
support enabled on gcc.
This fixes the linux-debug build.
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The assertion failed when we ran out of exec memory.
Found with conform texcombine test.
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This set of code changes are for stencil code generation
support. Both one-sided and two-sided stenciling are supported.
In addition to the raw code generation changes, these changes had
to be made elsewhere in the system:
- Added new "register set" feature to the SPE assembly generation.
A "register set" is a way to allocate multiple registers and free
them all at the same time, delegating register allocation management
to the spe_function unit. It's quite useful in complex register
allocation schemes (like stenciling).
- Added and improved SPE macro calculations.
These are operations between registers and unsigned integer
immediates. In many cases, the calculation can be performed
with a single instruction; the macros will generate the
single instruction if possible, or generate a register load
and register-to-register operation if not. These macro
functions are: spe_load_uint() (which has new ways to
load a value in a single instruction), spe_and_uint(),
spe_xor_uint(), spe_compare_equal_uint(), and spe_compare_greater_uint().
- Added facing to fragment generation. While rendering, the rasterizer
needs to be able to determine front- and back-facing fragments, in order
to correctly apply two-sided stencil. That requires these changes:
- Added front_winding field to the cell_command_render block, so that
the state tracker could communicate to the rasterizer what it
considered to be the front-facing direction.
- Added fragment facing as an input to the fragment function.
- Calculated facing is passed during emit_quad().
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