Age | Commit message (Collapse) | Author | |
---|---|---|---|
2009-01-05 | cell: fix code emit for RSQ/RCP when src arg == dst arg | Brian Paul | |
Fixes moire-like artifacts seen in fslight demo. | |||
2009-01-04 | cell: initial codegen support for fragment shader loops | Brian Paul | |
Basic for/while loops work now. Only one level of loop nesting is supported at this time (same for if/else). The progs/glsl/mandelbrot demo works, but the colors are too dim. | |||
2009-01-04 | cell: clean-up, improve SPU code generation | Brian Paul | |
Start on ARL and address-relative indexing too. | |||
2008-11-11 | cell: implement NRM3 opcode | Brian Paul | |
2008-10-29 | cell: add scalar param to emit_function_call() to indicate scalar function calls | Brian Paul | |
Scalar calls only use the X component of the src regs and smear the result across the dest register's X/Y/Z/W. | |||
2008-10-22 | cell: note that dst reg writing needs clamping | Brian Paul | |
2008-10-16 | cell: implement KIL instruction | Brian Paul | |
2008-10-16 | cell: clean up various texture-related things | Brian Paul | |
Distinguish among texture targets in codegen. progs/demos/cubemap.c runs correctly now too. | |||
2008-10-14 | cell: fall-through case for TGSI_OPCODE_TXB | Brian Paul | |
2008-10-10 | cell: more instruction scheduling optimizations (MIN/MAX/LERP/etc) | Brian Paul | |
Also, optimize register->memory stores. | |||
2008-10-10 | cell: pass texture unit (sampler number) to txp() function | Brian Paul | |
The glsl/multitex demo runs now. | |||
2008-10-10 | cell: fix function prologue/epilogue code for large stack frames | Brian Paul | |
The ai instruction is limited to a 10-bit signed immediate value. | |||
2008-10-10 | cell: fix LERP when dst reg is a src reg | Brian Paul | |
Also, bump up frame size and fix some assertions. | |||
2008-10-10 | cell: fix fm/fs copy & paste bug from a few commits ago | Brian Paul | |
2008-10-10 | cell: fix bug in emit_FLR() when src reg == dst reg | Brian Paul | |
2008-10-10 | cell: fix bug in emit_FRC() when src register == dst register. | Brian Paul | |
With this fix, the glsl/brick demo runs. | |||
2008-10-09 | cell: implement basic TXP instruction in fragment shaders | Brian Paul | |
Lots of restrictions for now (one 2D texture, no mipmaps, etc.) for now but basic texture demos work. TEX, TXD, TXP do the same thing for the time being. | |||
2008-10-09 | cell: better immediate value allocation, better comments | Brian Paul | |
2008-10-09 | cell: massage the emit functions to get better instruction scheduling | Brian Paul | |
2008-10-08 | cell: implement function calls from shader code. fslight demo runs now. | Brian Paul | |
Used for SIN, COS, EXP2, LOG2, POW instructions. TEX next. Fixed some bugs in MIN, MAX, DP3, DP4, DPH instructions. In rtasm code: Special-case spe_lqd(), spe_stqd() functions so they take byte offsets but low-order 4 bits are shifted out. This makes things consistant with SPU assembly language conventions. Added spe_get_registers_used() function. | |||
2008-10-07 | cell: add support for fragment shader constant buffers | Brian Paul | |
2008-10-07 | cell: fix incorrect extended swizzle term code in get_src_reg() | Brian Paul | |
2008-10-07 | cell: fix formatting | Brian Paul | |
2008-09-26 | cell: checkpoint: more work in emit_function_call() | Brian Paul | |
Simple function call works now, but we don't save/restore the caller's registers yet. | |||
2008-09-26 | cell: checkpoint: support for function calls in SPU shaders | Brian Paul | |
Will be used for instructions like SIN/COS/POW/TEX/etc. The PPU needs to know the address of some functions in the SPU address space. Send that info to the PPU/main memory rather than patch up shaders on the SPU side. Not finished/tested yet... | |||
2008-09-22 | cell: Fixed bug with absolute, negate, set-negative logic in source fetch ↵ | Jonathan White | |
for TGSI instructions. The logic should operate on the origin channel not the swizzled channel. Please enter the commit message for your changes. | |||
2008-09-22 | cell: Added TRUNC, SWZ (extended) and XPD instructions, verified against ↵ | Jonathan White | |
softpipe. Optimized FLR and FRC. Fixed writeback logic for DP3, DP4 and DPH. | |||
2008-09-22 | cell: Added DPH instruction and verified against softpipe. | Jonathan White | |
2008-09-19 | cell: Added FRC instruction | Jonathan White | |
2008-09-19 | cell: Added FLR instruction. Verified the following instructions match ↵ | Jonathan White | |
softpipe: MOV, ADD, MUL, SGE, SUB, MAD, ABS, SLT, MIN, MAX, LRP, DP3, DP4, CMP, FLR | |||
2008-09-19 | cell: Fixed bugs with DP3 and DP4, they match softpipe results now. | Jonathan White | |
2008-09-19 | cell: change spe_complement() to take a src and dst reg, like other instructions | Brian Paul | |
2008-09-18 | cell: Added CMP instruction | Jonathan White | |
2008-09-18 | cell: Fix bug with complement logic for SGE and SLE | Jonathan White | |
2008-09-18 | cell: Added SGE and SLE instructions to dispatch function | Jonathan White | |
2008-09-18 | cell: Added SGE and SLE instructions | Jonathan White | |
2008-09-16 | cell: Added RCP and RSQ instruction support. | Jonathan White | |
2008-09-16 | cell: Added DP3 and DP4 instructions | Jonathan White | |
2008-09-16 | cell: Optimized LERP with fma | Jonathan White | |
Please enter the commit message for your changes. | |||
2008-09-16 | cell: Fixed MIN/MAX algorithm | Jonathan White | |
2008-09-15 | cell: export CELL_DEBUG=asm to dump SPU assembly code | Brian Paul | |
2008-09-15 | cell: Added LERP instruction | Jonathan White | |
2008-09-15 | cell: Added support for SLT, SEQ and SNE instructions | Jonathan White | |
2008-09-15 | cell: Added support for ABS instruction | Jonathan White | |
2008-09-15 | Added support for SUB and MAD instructions | Jonathan White | |
2008-09-13 | cell: implement negation, absolute value and set-sign for src regs in code gen | Brian Paul | |
2008-09-12 | cell: remove old disassembly/dump code; use dumper code in SPE emitter. | Brian Paul | |
2008-09-12 | cell: implement DDX/DDY codegen (untested) | Brian Paul | |
2008-09-12 | cell: implement TGSI immediates in SPE code generator | Brian Paul | |
2008-09-12 | cell: initial support for IF/ELSE/ENDIF in fragment shader codegen | Brian Paul | |
Only one level of if/else/endif nesting is currently working. |