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Fewer float/int conversions involved.
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Plus, clearer shuffle masks in other funcs.
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Also, optimize register->memory stores.
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The glsl/multitex demo runs now.
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The ai instruction is limited to a 10-bit signed immediate value.
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These are the defects found and fixed so far. Several more have
been observed; I'm working on them.
- Fixed an error in spe_load_uint() that caused incorrect values to be
loaded if the given unsigned value had the low 18 bits as 0,
and that caused inefficient code to be emitted if the given value
had the high 14 bits as 0.
- Fixed a problem in stencil code generation where optional registers
weren't tracked correctly.
- Fixed a problem that the stencil function NEVER was acting as ALWAYS.
- Fixed several problems that could occur if stenciling were enabled but
depth was disabled.
- Fixed a problem with two-sided stencil writemask handling that could
cause a stencil writemask to not be applied.
- Fixed several state permutations that were incorrectly flagged as
not requiring stencil values to be calculated.
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Ensures that SPUs are initialized/ready before proceeding.
This fixes a spurious assertion failure when the SPU-side shader function info
hasn't been returned to the PPU before shader codegen.
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Also, bump up frame size and fix some assertions.
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With this fix, the glsl/brick demo runs.
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Lots of restrictions for now (one 2D texture, no mipmaps, etc.) for now
but basic texture demos work.
TEX, TXD, TXP do the same thing for the time being.
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Used for SIN, COS, EXP2, LOG2, POW instructions. TEX next.
Fixed some bugs in MIN, MAX, DP3, DP4, DPH instructions.
In rtasm code:
Special-case spe_lqd(), spe_stqd() functions so they take byte offsets but
low-order 4 bits are shifted out. This makes things consistant with SPU
assembly language conventions.
Added spe_get_registers_used() function.
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This set of code changes are for stencil code generation
support. Both one-sided and two-sided stenciling are supported.
In addition to the raw code generation changes, these changes had
to be made elsewhere in the system:
- Added new "register set" feature to the SPE assembly generation.
A "register set" is a way to allocate multiple registers and free
them all at the same time, delegating register allocation management
to the spe_function unit. It's quite useful in complex register
allocation schemes (like stenciling).
- Added and improved SPE macro calculations.
These are operations between registers and unsigned integer
immediates. In many cases, the calculation can be performed
with a single instruction; the macros will generate the
single instruction if possible, or generate a register load
and register-to-register operation if not. These macro
functions are: spe_load_uint() (which has new ways to
load a value in a single instruction), spe_and_uint(),
spe_xor_uint(), spe_compare_equal_uint(), and spe_compare_greater_uint().
- Added facing to fragment generation. While rendering, the rasterizer
needs to be able to determine front- and back-facing fragments, in order
to correctly apply two-sided stencil. That requires these changes:
- Added front_winding field to the cell_command_render block, so that
the state tracker could communicate to the rasterizer what it
considered to be the front-facing direction.
- Added fragment facing as an input to the fragment function.
- Calculated facing is passed during emit_quad().
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Simple function call works now, but we don't save/restore the caller's registers yet.
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Will be used for instructions like SIN/COS/POW/TEX/etc. The PPU needs to
know the address of some functions in the SPU address space. Send that
info to the PPU/main memory rather than patch up shaders on the SPU side.
Not finished/tested yet...
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The colormask code generation had assumed that its input packed pixels were
in RGBA format. In fact, the format they're in is dependent on the
pipe color format.
Now the color format is passed in to gen_colormask(), and proper
color format-dependent SPU code is generated.
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for TGSI instructions. The logic should operate on the origin channel not the swizzled channel.
Please enter the commit message for your changes.
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softpipe. Optimized FLR and FRC. Fixed writeback logic for DP3, DP4 and DPH.
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32-byte boundary
To make sure even/odd instructions hit the right pipes.
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softpipe: MOV, ADD, MUL, SGE, SUB, MAD, ABS, SLT, MIN, MAX, LRP, DP3, DP4, CMP, FLR
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Also: improve float/int Z conversion.
Use clgt instead of cgt in depth test since we're comparing unsigned values.
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