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If we create multiple instances of an nv50_reg referencing
them same resource, register allocation from alloc_reg has
to be done with the original nv50_reg.
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Also fixes RSQ of negative sources.
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This negation would only be triggered in situations
where it's incorrect.
The caller of set_immd should negate the immediate value
in the instruction itself if desired, and will also know
if it's a float or an int.
ADD TEMP[0], CONST[0], -IMMD[0] would load the immediate
into extra TEMP, negated, and set the negate flag in add
as well - double negation.
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Signed-off-by: Francisco Jerez <currojerez@riseup.net>
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It doesn't seem to be possible to set the egdeflag in the
vertex shader, so we need to fallback to pushing vertices
through the FIFO and use method 0x15e4 if they are used.
This only works if VP does MOV OUT[X] IN[Y] where X is the
edgeflag output, and Y is saved so we can tell the correct
input later.
The VP still writes the useless values to wasted outputs
as punishment.
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The state tracker now does the correct thing, so
interpret negation normally.
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Before I tried to distinguish int +0 and -0, and regs
relative to $a1 would have been considered reserved
for TGSI.
This would probably never occur, let it be fixed even so.
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This is easier, we don't have to record all the BRK branches
to fill in the address at ENDLOOP - which wasn't done before
and thus made all but the last BRK branch jump to the start.
Also, we don't risk reactivting threads that already left
the loop if we join threads after a conditional with a BRK
(although it might be wiser to remove the join altogether
in such cases).
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Trying to free part of nv50_pc->reg_instances[] for an
nv50_reg representing an indirect constant resulted in
a segmentation fault.
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Sometimes we want non-float immediates, hacking them into
floats isn't nice.
Sorry, this should have already been committed before.
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If lod or bias can be non-constant across a quad of fragments,
we need to execute TEX separately for each value.
Don't ask why.
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... and don't set the 'live' flag for TEX anymore, we'd
have to know if results affect the inputs for another TEX,
and I'm not going to do that kind of analysis now.
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So we can use the 'mod' member without concern
if a source is used multiple times in 1 insn.
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Conflicts:
src/gallium/drivers/r300/r300_vs.c
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For each FP input, don't assume that the VP output will be
at the same position, but scan the semantics instead, then
put the correct output reg indices into VP_RESULT_MAP.
Position is still assumed to be the first output/input.
See 07fafc7c9346aa260829603bf3188596481e9e62, which renders
previous assumptions incorrect.
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Simplifies things since the second to last one will then
be converted in the subsequent pass that ensures alignment
automatically.
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SrcRegister -> Register
SrcRegisterInd -> Indirect
SrcRegisterDim -> Dimension
SrcRegisterDimInd -> DimIndirect
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DstRegister -> Register
DstRegisterInd -> Indirect
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DeclarationRange -> Range
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InstructionPredicate -> Predicate
InstructionLabel -> Label
InstructionTexture -> Texture
FullSrcRegisters -> Src
FullDstRegisters -> Dst
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Rename Semantic.SemanticName to Semantic.Name. Similar for
SemanticIndex, and the members of the tgsi_version struct.
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It would be nice if these drivers built under the linux-debug header
so that these types of interface changes can be minimally propogated
into those drivers by people without the hardware. They don't have to
generate a working driver -- though a command-dumping winsys would be
an excellent for regression checking.
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Don't assume that a SET that writes to IF's argument
directly precedes the IF.
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Will use AND for gl_FrontFacing, the face input
is either 0 or 0xffffffff.
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Adds a more generic SIFC transfer function.
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We have to indicate to the hw whether the FP exports
multiple colour results.
Method 0x121c is used to specify the number of RTs.
Also deactivate zeta explicitly if there's no zsbuf.
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We should really learn to not waste so many though.
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Contained some rather obvious thinking errors before,
and didn't consider offsets from TGSI ADDRESS regs.
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These haven't been used by the mesa state tracker since the
conversion to tgsi_ureg, and it seems that none of the
other state trackers are using it either.
This helps simplify one of the biggest suprises when starting off with
TGSI shaders.
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Allow indirect uniform access and increase the
limit on parameters from 128 to 512.
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We only have a per nv50_reg negation flag, if an
nv50_reg is used more than once in a TGSI op with
different sign modes, we'd generate wrong code.
We probably can't do much better without more
invasive changes.
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If you e.g. only need alpha, it ends up in the first reg,
not the last, as it would when reading rgb too.
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Separated the integer rounding mode flag for cvt.
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There's a good chance a loop won't execute correctly
though since our TEMP allocation assumes programs to
be executed linearly. Will fix later.
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