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NOUVEAU_BO_RD is defined (1 << 2), and `|' has higher precedence than `?'
so the second argument of nouveau_bo_map was always 0.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
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This should be the default setting.
See also 7d967b9b7c08aea2a471c5bf6aced8bfafdae874.
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Mip-mapped 3D textures are not arrays of 2D layers
with a mip-map layout like 2D textures, therefore we
cannot use image_nr == depth for them.
Making use of "volume tiling" modes now, the allowed
modes are 0xZY where Z <= 5 and y <= 5.
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Don't assume that a SET that writes to IF's argument
directly precedes the IF.
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Will use AND for gl_FrontFacing, the face input
is either 0 or 0xffffffff.
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First, using width * block size as pitch is evidently
wrong if a block contains more than 1 texel.
For tiled textures, since a block occupies a contiguous
area of memory, y addressing in m2mf has to be done by
block index, not the y coordinate itself.
This should fix compressed textures.
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Adds a more generic SIFC transfer function.
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We have to indicate to the hw whether the FP exports
multiple colour results.
Method 0x121c is used to specify the number of RTs.
Also deactivate zeta explicitly if there's no zsbuf.
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Some cards have crippling defaults set and use only 4
of 32 lanes. This should activate 16 on these.
Those that allow 32 by default should still do so.
Found out by Marcin Kościelnicki.
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We should really learn to not waste so many though.
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Contained some rather obvious thinking errors before,
and didn't consider offsets from TGSI ADDRESS regs.
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These haven't been used by the mesa state tracker since the
conversion to tgsi_ureg, and it seems that none of the
other state trackers are using it either.
This helps simplify one of the biggest suprises when starting off with
TGSI shaders.
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Set the same bits as for linear filtering (in addition
to max anisotropy), and 2 unknown bits I've seen set.
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Allow indirect uniform access and increase the
limit on parameters from 128 to 512.
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We only have a per nv50_reg negation flag, if an
nv50_reg is used more than once in a TGSI op with
different sign modes, we'd generate wrong code.
We probably can't do much better without more
invasive changes.
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Requesting a new real buffer from the kernel and
copying all the data is wasteful e.g. if only a
few (but widely spread) vertices are accessed.
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Add proper flushes for TIC and TSC and remove
the costly 2D.0110 flush in nv50_flush.
Correct TIC and TSC bo sizes.
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Similar to nv40.
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Tested with progs/demos/multiarb.
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Always test for PIPE_TRANSFER_READ/WRITE using the bit-wise and operator, and
add a pipe_transfer_buffer_flags() helper for getting the buffer usage flags
corresponding to them.
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If you e.g. only need alpha, it ends up in the first reg,
not the last, as it would when reading rgb too.
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Until now, only primitives wholly outside the view volume
were not drawn.
This was only visibile when using a viewport smaller than
the window size, naturally.
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Separated the integer rounding mode flag for cvt.
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There's a good chance a loop won't execute correctly
though since our TEMP allocation assumes programs to
be executed linearly. Will fix later.
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No longer used. S3TC support is queried via
pipe_screen::is_format_supported.
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- And reduce RING_SPACE to 2, instead of 3.
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When swapping sources 0 and 1, EQ of course does *not*
become NE, etc.
Introduced in 2b963f5c723401aa2646bd48eefe065cd335e280.
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Allocation is unnecessary since all uniforms are
uploaded on every constant buffer change anyway.
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This moves construction of the mapping between VP outputs
and FP inputs into validation.
The map also contains slots for special outputs like clip
distance and point size, so we need to at least merge the
VP related and FP related parts on validation if we want
to support those.
Now we match every single FP input component with results
from the VP and leave those not read out of the map, or
replace those not written by 0 (xyz) or 1 (w).
The bitmap indicating linear interpolants is also filled,
and flat FP inputs are mapped in only after non-flat ones,
as is required.
Furthermore, we can save some space by only fetching VP
attrs we actually use, and avoid wasting any output regs
because of TGSI using less than 4 components.
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Make use of tgsi_shader_info to determine how many nv50_regs we
need to allocate, whether program uses KIL, or writes DEPR.
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