| Age | Commit message (Collapse) | Author |
|---|
|
- Added flush notify functions for NV30 and NV40.
- Flushing mid frame will call flush notify, which will resubmit all
relocs.
- We don't try to recover from reloc failure yet.
|
|
Trying to free part of nv50_pc->reg_instances[] for an
nv50_reg representing an indirect constant resulted in
a segmentation fault.
|
|
Sometimes we want non-float immediates, hacking them into
floats isn't nice.
Sorry, this should have already been committed before.
|
|
|
|
|
|
|
|
If lod or bias can be non-constant across a quad of fragments,
we need to execute TEX separately for each value.
Don't ask why.
|
|
... and don't set the 'live' flag for TEX anymore, we'd
have to know if results affect the inputs for another TEX,
and I'm not going to do that kind of analysis now.
|
|
|
|
Unfortunately it seems that if depth comparison is
active and we read a 2D texture, i.e. provide only
2 inputs, the second is used for comparison ...
|
|
|
|
Keeping this dynamically allocated for texture arrays.
Since we don't use it to store zslice offsets anymore
it's either 1 or 6 integers (cube) ...
|
|
So we can use the 'mod' member without concern
if a source is used multiple times in 1 insn.
|
|
|
|
|
|
Conflicts:
src/gallium/state_trackers/xorg/xorg_exa.c
|
|
|
|
Conflicts:
src/gallium/drivers/r300/r300_vs.c
|
|
|
|
We need to update VP_RESULT_MAP and/or COORD_REPLACE_MAP
when light_twoside and/or point_sprite are changed.
|
|
For each FP input, don't assume that the VP output will be
at the same position, but scan the semantics instead, then
put the correct output reg indices into VP_RESULT_MAP.
Position is still assumed to be the first output/input.
See 07fafc7c9346aa260829603bf3188596481e9e62, which renders
previous assumptions incorrect.
|
|
|
|
Simplifies things since the second to last one will then
be converted in the subsequent pass that ensures alignment
automatically.
|
|
The hardware wants the pattern the same way it is
passed to glPolygonStipple.
|
|
width/height/depth arrays
|
|
SrcRegister -> Register
SrcRegisterInd -> Indirect
SrcRegisterDim -> Dimension
SrcRegisterDimInd -> DimIndirect
|
|
DstRegister -> Register
DstRegisterInd -> Indirect
|
|
DeclarationRange -> Range
|
|
InstructionPredicate -> Predicate
InstructionLabel -> Label
InstructionTexture -> Texture
FullSrcRegisters -> Src
FullDstRegisters -> Dst
|
|
Rename Semantic.SemanticName to Semantic.Name. Similar for
SemanticIndex, and the members of the tgsi_version struct.
|
|
It would be nice if these drivers built under the linux-debug header
so that these types of interface changes can be minimally propogated
into those drivers by people without the hardware. They don't have to
generate a working driver -- though a command-dumping winsys would be
an excellent for regression checking.
|
|
|
|
This should be the default setting.
See also 7d967b9b7c08aea2a471c5bf6aced8bfafdae874.
|
|
|
|
|
|
Mip-mapped 3D textures are not arrays of 2D layers
with a mip-map layout like 2D textures, therefore we
cannot use image_nr == depth for them.
Making use of "volume tiling" modes now, the allowed
modes are 0xZY where Z <= 5 and y <= 5.
|
|
|
|
Don't assume that a SET that writes to IF's argument
directly precedes the IF.
|
|
Will use AND for gl_FrontFacing, the face input
is either 0 or 0xffffffff.
|
|
First, using width * block size as pitch is evidently
wrong if a block contains more than 1 texel.
For tiled textures, since a block occupies a contiguous
area of memory, y addressing in m2mf has to be done by
block index, not the y coordinate itself.
This should fix compressed textures.
|
|
Adds a more generic SIFC transfer function.
|
|
We have to indicate to the hw whether the FP exports
multiple colour results.
Method 0x121c is used to specify the number of RTs.
Also deactivate zeta explicitly if there's no zsbuf.
|
|
Some cards have crippling defaults set and use only 4
of 32 lanes. This should activate 16 on these.
Those that allow 32 by default should still do so.
Found out by Marcin Kościelnicki.
|
|
|
|
|
|
We should really learn to not waste so many though.
|
|
Contained some rather obvious thinking errors before,
and didn't consider offsets from TGSI ADDRESS regs.
|
|
|
|
These haven't been used by the mesa state tracker since the
conversion to tgsi_ureg, and it seems that none of the
other state trackers are using it either.
This helps simplify one of the biggest suprises when starting off with
TGSI shaders.
|
|
Set the same bits as for linear filtering (in addition
to max anisotropy), and 2 unknown bits I've seen set.
|
