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This fixes all S3TC piglit/texwrap tests.
NOTE: This is a candidate for the 7.9 branch.
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On my rv530 at least HiZ is causing rendering issues in gears.
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This implements fast Z clear, Z compression, and HiZ support for r300->r500
GPUs.
It also allows cbzb clears when fast Z clears are being used for the ZB.
It requires a kernel with hyper-z support.
Thanks to Marek Olšák <maraeo@gmail.com>, who started this off, and Alex Deucher at AMD for providing lots of hints.
v2:
squashed zmask ram size fix]
squashed r300g/blitter: fix Z readback when compressed]
v3:
rebase around texture changes in master - .1 fix more bits
v4:
migrated to using u_mm in r300_texture to manage hiz/zmask rams consistently
disabled HiZ when using OQ
flush z-cache before turning hyper-z off
update hyper-z state on dsa state change
store depthclearvalue across cbzb clears and replace it afterwards.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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RV3xx is 2, RV560,RV570 is 8
Noticed by Tormod Volden.
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As per Radeon 9700 Opengl Programming and Optimization Guide [1], there are
16 texture units even on the first r300 chipsets. If you think I am wrong,
feel free to propose a patch.
[1] Here's PDF: http://people.freedesktop.org/~mareko/
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We really need to get these into bug reports.
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As suggested by agd5f.
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r4xx has some additional fragment shader registers compared to r3xx.
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This name is totally subject to change if ever I need to separate R3xx
for some other reason.
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This reverts commit 6a40d1e9d96f8e8c57bc3bbd6f567cacd4471f59.
Turns out that we *do* need these for OQ after all. Go figure.
Conflicts:
src/gallium/winsys/drm/radeon/core/radeon_r300.h
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Per 74cb2aba on xf86-video-ati.
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See the previous commit for an explanation. This is just all the support code
for GB_TILE_CONFIG.
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Wow, how long's that been there? Embarrassing.
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Just like R300_NO_TCL, when set, forces HW TCL off.
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The debug functions depend on several util function for os abstractions, and
these depend on debug functions, so a seperate module is not possible.
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Signed-off-by: Corbin Simpson <MostAwesomeDude@gmail.com>
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It's not "pipes", it's floating-point vertex processors. Completely different.
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Ah, my code's so bad. It's amazing.
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Whoo, stuff is starting to look cleaner and cleaner.
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Step two: Integration. Yay?
Time to stop messing around with this and actually go do things.
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Part one: Capabilities from classic Mesa.
Damn, if only we didn't have so many fucking Radeons!
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