Age | Commit message (Collapse) | Author |
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Add explicit EVENT_TYPE field
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Discard fractional bits from linewidth. This matches the nvidia
closed drivers, my reading of the OpenGL SI and current llvmpipe
behaviour.
It looks a lot nicer & avoids ugliness where lines alternate between n
and n+1 pixels in width along their length.
Also fix up r600g to match.
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this sets up a single loop constant like r600c does.
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just a typo in the register headers.
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there are some vertex formats defined in r600c not in the docs.
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These need to be emitted, we also need them to do proper vtx start,
instead of abusing index offset.
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although evergreen can apparantly sample direct from 24-bit,
just make it work with the current method for now.
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Build packet header once and allow to add fake register support so
we can handle things like indexed set of register (evergreen sampler
border registers for instance.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Doesn't bother fixing old path code, just disable that reg.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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adds the sscaled formats, this passes some more of the draw-vertices tests.
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This doesn't work yet.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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evergreen is always the same as r700 here.
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adds shader opcodes + assembler support (except ARL)
uses constant buffers
add interp instructions in fragment shader
adds all evergreen hw states
adds evergreen pm4 support.
this runs gears for me on my evergreen
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