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path: root/src/gallium/drivers/r600/r600.h
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2011-03-01r600g: add NV_conditional_render support.Dave Airlie
This is reliant on a drm patch that I posted on the list + a version bump. These will appear in drm-next today. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-01r600g: start using drm minor version to enable things.Dave Airlie
If the drm minor version is > 9 (i.e. whats in drm-next), we enable s3tc + texture tiling by default now. this changes R600_FORCE_TILING to R600_TILING which can be set to false to disable tiling on working drm. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-28r600g: indentation fixesJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2011-01-31r600g: fix OQ on evergreenAlex Deucher
6xx/7xx have a max of 4 DBs, evergreen have a max of 8. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-31r600g: fix occlusion query results.Dave Airlie
Like on some r5xx, there are multiple DB backends on the r600, we need to add up the query results from each of these to get the final correct value. So far I'm not 100% sure how to calculate the num_db, value setting it to 4 should be harmless enough until we do. This fixes occulsion_query piglit test on my rv740. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-01-25r600g: Implement timer queries.Mathias Fröhlich
2011-01-11r600g: move user fence into base radeon structureJerome Glisse
This avoid any issue when context is free and we still try to access fence through radeon structure. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2011-01-06r600g: add support for NI (Northern Islands) GPUsAlex Deucher
This adds support for Barts, Turks, and Caicos asics.
2010-12-23r600g: Rearrange print order of outputs of R600_ERR.Vinson Lee
2010-12-22r600g: drop unused code in evergreen.Dave Airlie
this code was pretty much duplicated, thanks to Henri Verbeet on irc for pointing it out. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-03r600g: more indentation fix + warning silencing + dead code removalJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-22r600g: add support for ontario APUsAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-11-19r600g: add fetch shader capabilitiesJerome Glisse
Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-11-08r600g: implement texture_get_handle (needed for eglExportDRMImageMESA)Benjamin Franzke
2010-11-03r600g: propogate resource usage flags to winsys, use to choose bo domainsKeith Whitwell
This opens the question of what interface the winsys layer should really have for talking about these concepts. For now I'm using the existing gallium resource usage concept, but there is no reason not use terms closer to what the hardware understands - eg. the domains themselves.
2010-10-18r600g: retrieve tiling info from kernel for shared buffers.Dave Airlie
we need to know if the back is tiled so we can blit from it properly.
2010-10-18r600g: get tiling info from kernelDave Airlie
2010-10-05r600g: userspace fence to avoid kernel call for testing bo busy statusJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-05r600g: simplify block relocationJerome Glisse
Since flush rework there could be only one relocation per register in a block. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-05r600g: use dirty list to track dirty blocksBas Nieuwenhuizen
Got a speed up by tracking the dirty blocks in a seperate list instead of looping through all blocks. This version should work with block that get their dirty state disabled again and I added a dirty check during the flush as some blocks were already dirty.
2010-10-05r600g: improve bo flushingJerome Glisse
Flush read cache before writting register. Track flushing inside of a same cs and avoid reflushing same bo if not necessary. Allmost properly force flush if bo rendered too and then use as a texture in same cs (missing pipeline flush dunno if it's needed or not). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04r600g: allow r600_bo to be a sub allocation of a big boJerome Glisse
Add bo offset everywhere needed if r600_bo is ever a sub bo of a bigger bo. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04r600g: rename radeon_ws_bo to r600_boJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-29r600g: delete old pathJerome Glisse
Lot of clean can now happen. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-29r600g: use a hash table instead of groupJerome Glisse
Instead of creating group of register use a hash table to lookup into which block each register belongs. This simplify code a bit. Signed-off-by: Jerome Glisse <jglisse@redhat.com
2010-09-28r600g: suspend/resume occlusion query around clear/copyJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-27r600g: build packet header onceJerome Glisse
Build packet header once and allow to add fake register support so we can handle things like indexed set of register (evergreen sampler border registers for instance. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-27r600g: add evergreen texture resource properly.Dave Airlie
adding sampler border looks impossible with current design, another day, another corner case not worked out.
2010-09-26r600g: disable early cull optimization when occlusion query runningJerome Glisse
When occlusion query are running we want to have accurate fragment count thus disable any early culling optimization GPU has. Based on work from Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-23r600g: initial evergreen support in new pathJerome Glisse
This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-21r600g: occlusion query for new designJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-21r600g: directly allocate bo for user bufferJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-20r600g: move chip class to radeon common structureJerome Glisse
So texture code can be shared btw new state design & old one. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-19r600g: Buffer object maps imply a wait.Henri Verbeet
Unless e.g. PB_USAGE_DONTBLOCK or PB_USAGE_UNSYNCHRONIZED would be specified.
2010-09-17r600g: alternative command stream building from contextJerome Glisse
Winsys context build a list of register block a register block is a set of consecutive register that will be emited together in the same pm4 packet (the various r600_block* are there to provide basic grouping that try to take advantage of states that are linked together) Some consecutive register are emited each in a different block, for instance the various cb[0-7]_base. At winsys context creation, the list of block is created & an index into the list of block. So to find into which block a register is in you simply use the register offset and lookup the block index. Block are grouped together into group which are the various pkt3 group of config, context, resource, Pipe state build a list of register each state want to modify, beside register value it also give a register mask so only subpart of a register can be updated by a given pipe state (the oring is in the winsys) There is no prebuild register list or define for each pipe state. Once pipe state are built they are bound to the winsys context. Each of this functions will go through the list of register and will find into which block each reg falls and will update the value of the block with proper masking (vs/ps resource/constant are specialized variant with somewhat limited capabilities). Each block modified by r600_context_pipe_state_set* is marked as dirty and we update a count of dwords needed to emit all dirty state so far. r600_context_pipe_state_set* should be call only when pipe context change some of the state (thus when pipe bind state or set state) Then to draw primitive you make a call to r600_context_draw void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw) It will check if there is enough dwords in current cs buffer and if not will flush. Once there is enough room it will copy packet from dirty block and then add the draw packet3 to initiate the draw. The flush will send the current cs, reset the count of dwords to 0 and remark all states that are enabled as dirty and recompute the number of dwords needed to send the current context. Signed-off-by: Jerome Glisse <jglisse@redhat.com>