Age | Commit message (Collapse) | Author |
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Join multiple exports into just one instruction
instead of exporting each register separately.
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eea1d8199b376f37027c14669e0bdf991a22872d
Although CUBE is a reduction inst, it writes to more than just PV.X
so we need to keep the dst channel.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This fixes:
- piglit/draw-vertices
- piglit/draw-vertices-half-float
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FLT_TO_INT is a vector instruction, despite what the (current) documentation
says. FLT_TO_INT_FLOOR and FLT_TO_INT_RPI aren't explicitly mentioned in the
documentation, but those are vector instructions too.
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Add missing evergreen FLT_TO_INT_FLOOR instruction.
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According to R700 ISA we have only two channels for cfile constants.
This patch makes piglit tests "glsl1-constant array with constant
indexing" happy on RV710.
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If a literal slot isn't used it should be set
to 0 instead of an uninitialized value. Also the
channels for pre R700 trig functions were incorrect.
And most important literals were not counted against ndw,
resulting in an invalid force_add_cf detection.
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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needed for asic specific opcodes
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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The usage of macro V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR was
introduced by commit 323ef3a1f07ba4333dadebab571ddcd49d95f45c but the
macro is undefined. Disable this case to fix the build for now.
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Fixes SCons build.
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If last instruction is an CF_INST_ALU we don't need to emit an
additional CF_INST_POP for stack clean up after an IF ELSE ENDIF.
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r600_bc_add_alu_type().
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This adds support for Barts, Turks, and Caicos asics.
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From the r600 ISA:
Each ALU clause can lock up to four sets of constants
into the constant cache. Each set (one cache line) is
16 128-bit constants. These are split into two groups.
Each group can be from a different constant buffer
(out of 16 buffers). Each group of two constants consists
of either [Line] and [Line+1] or [line + loop_ctr]
and [line + loop_ctr +1].
For supporting more than 64 constants, we need to
break the code into multiple ALU clauses based
on what sets of constants are needed in that clause.
Note: This is a candidate for the 7.10 branch.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Vertex elements change are less frequent than draw call, those to
avoid rebuilding fetch shader to often build the fetch shader along
vertex elements. This also allow to move vertex buffer setup out
of draw path and make update to it less frequent.
Shader update can still be improved to only update SPI regs (based
on some rasterizer state like flat shading or point sprite ...).
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Makes the code much clearer.
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Use fetch shader instead of having fetch instruction in the vertex
shader. Allow to restrict shader update to a smaller part when
vertex buffer input layout changes.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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[airlied: remove unused vars]
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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since we plan on using dx10 constant buffers everywhere.
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this shouldn't change behaviour, just push the choice of what
to do out to the shader.
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Lot of clean can now happen.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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we still have constants to add and next int may need also 6 slots
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running piglit's texrect-many caused the vtx to overflow.
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