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Reviewed-by: Henri Verbeet <hverbeet@gmail.com>
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The r600_bc_alu_src structure is used in two different ways, as a vector and
for the individual channels of that same vector. This is somewhat fragile,
and probably confusing.
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This is much easier to work with, and allows use to get rid of some of the
literal handling hacks.
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Join multiple exports into just one instruction
instead of exporting each register separately.
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Vertex elements change are less frequent than draw call, those to
avoid rebuilding fetch shader to often build the fetch shader along
vertex elements. This also allow to move vertex buffer setup out
of draw path and make update to it less frequent.
Shader update can still be improved to only update SPI regs (based
on some rasterizer state like flat shading or point sprite ...).
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Use fetch shader instead of having fetch instruction in the vertex
shader. Allow to restrict shader update to a smaller part when
vertex buffer input layout changes.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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[airlied: remove unused vars]
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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since we plan on using dx10 constant buffers everywhere.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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this shouldn't change behaviour, just push the choice of what
to do out to the shader.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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On r6xx if an MOVA instruction is emitted we should set this bit.
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Avoid using r600_screen structure to get ptr to radeon
winsys structure.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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adds shader opcodes + assembler support (except ARL)
uses constant buffers
add interp instructions in fragment shader
adds all evergreen hw states
adds evergreen pm4 support.
this runs gears for me on my evergreen
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this is ported from r600c mostly, bank swizzling is real messy and I don't think
I got enough sleep last night to fully understand it.
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DX9 constants were in the constant file, and evergreen no longer support
cfile. r600/700 can also use constants in memory buffers, so add the code
(disabled for now) to enable that as precursor for evergreen.
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passes another ~20 piglits.
/me starts to run out low hanging fruit around now.
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Adds BGNLOOP, BRK, CONT, ENDLOOP support, ported from r600c.
17 piglits more on r300g.tests.
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this adds handling for some more CF instructions and conditions
also adds parameter for stack size emission
These seem to pass on VS with the stack size hack but not on FS,
TODO: fix FS + stack size calcs
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Make sure LIT fills all slot for instruction (can't do W instruction
without having the Z slot filled with at least a NOP).
ALU instruction can't access more than 4 constant, move constant to
temporary reg if we reach the limit.
Fix ALU block splitting, only split ALU after ALU with last instruction
bit sets.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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This add texture support to the assembler, generated code is
wrong (tested against working dump).
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Writing a compiler is time consuming and error prone in
order to allow r600g to further progress in the meantime
i wrote a simple tgsi assembler, it does stupid thing but
i would rather keep the code simple than having people
trying to optimize code it does.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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