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path: root/src/gallium/drivers/r600
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2011-03-25android: fix buildingChia-I Wu
2011-03-15r600g: FLT_TO_INT_FLOOR and FLT_TO_INT_RPI are vector-only instructions on ↵Henri Verbeet
Evergreen. Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-14r600g: don't set per-MRT blend bits on R600Alex Deucher
It doesn't support them. Also, we shouldn't be emitting CB_BLENDx_CONTROL on R600 as the regs don't exist there, but I'm not sure of the best way to deal with this in the current r600 winsys. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-03-14r600g: Original R600 does not support per-MRT blendsAlex Deucher
Only rv6xx+ support them. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-03-14r600g: Properly update MULTIWRITE_ENABLE in r600_pipe_shader_ps().Henri Verbeet
This sort of worked because blend state setup cleared MULTIWRITE_ENABLE again, but that's not something we want to depend on. Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-14r600g: Fix the DB_SHADER_CONTROL mask in create_ds_state().Henri Verbeet
Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-14r600g: Properly update DB_SHADER_CONTROL in evergreen_pipe_shader_ps().Henri Verbeet
Disable Z_EXPORT / STENCIL_EXPORT / KILL_ENABLE again if a shader doesn't use those. This is similar to 0a6f09a76a416b8672e149c520aa5bef33174223. Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-14r600g: Move fetch shader register setup to r600_state.c / evergreen_state.c.Henri Verbeet
Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-14r600g: Move r600_pipe_shader_ps() to r600_state.c.Henri Verbeet
Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-14r600g: Move r600_pipe_shader_vs() to r600_state.c.Henri Verbeet
The idea behind this is that anything touching registers should be in r600_state.c or evergreen_state.c. This is also consistent with evergreen_pipe_shader_vs(). Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-14r600g: Evergreen add support for log opcode.Rafael Monica
Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-13r600g: Only update DB_SHADER_CONTROL once in r600_pipe_shader_ps().Mathias Fröhlich
Avoid setting the same gpu register several times in a r600_pipe_state. Compute the final value of the register and set that one time. This avoids some overhead in r600_context_pipe_state_set(). Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de> Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-12r600g: Fix VS sampler view offsets for r600/r700.Carl-Philip Hänsch
077c448d184799e0d9ec962013ec784c6a5c1807 missed this. Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-12r600g: Fix an unused variable warning.Henri Verbeet
2011-03-11r600g: revert unintentional commitAdam Jackson
2011-03-11r600: Build fixAdam Jackson
r600_dri.so.tmp: undefined reference to `_mesa_rgba_logicop_enabled'
2011-03-11gallium: remove flags from the flush functionMarek Olšák
The drivers have been changed so that they behave as if all of the flags were set. This is already implicit in most hardware drivers and required for multiple contexts. Some state trackers were also abusing the PIPE_FLUSH_RENDER_CACHE flag to decide whether flush_frontbuffer should be called. New flag ST_FLUSH_FRONT has been added to st_api.h as a replacement.
2011-03-11gallium: remove the geom_flags param from is_format_supportedMarek Olšák
2011-03-11gallium: kill is_resource_referencedMarek Olšák
Only st/xorg used it and even incorrectly with regards to pipelined transfers.
2011-03-09r600g: remove some now unneeded code from r600_bc_vtx_buildChristian König
2011-03-09r600g: R700+ can do more than 8 tex and vtx clause in one CF instChristian König
Reviewed-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-09r600g: split R600 and R700 CF generation for VTX and TEXChristian König
Reviewed-by: Henri Verbeet <hverbeet@gmail.com>
2011-03-08r600g: set start instance correctlyChristian König
2011-03-07r600g: Simplify some swizzle lookups.Henri Verbeet
2011-03-07r600g: Constant buffers can contain up to 4096 constants.Henri Verbeet
2011-03-06r600g: use long long integers for instance addr calculationChristian König
Using a long for instance addr calculation isn't big enough on 32bit systems, use a long long int instead. Thanks to Rafael Monica for fixing this.
2011-03-05gallium: split CAP_INSTANCE_DRAWING into INSTANCEID and INSTANCE_DIVISORMarek Olšák
ARB_instanced_arrays is a subset of D3D9. ARB_draw_instanced is a subset of D3D10. The point of this change is to allow D3D9-level drivers to enable ARB_instanced_arrays without ARB_draw_instanced.
2011-03-05r600g: simplify instance addr calculationChristian König
Use MULHI_UINT instead of the more complex INT_TO_FLT->MUL->TRUNC->FLT_TO_INT
2011-03-05r600g: fix fragment shader size calculationChristian König
bc.ndw is altered in r600_bc_build, respect that in fragment shader size calculation.
2011-03-04r600g: disable tiling by default again.Dave Airlie
we still have a lot of corner cases that aren't working. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-03r600g: correct mega_fetch_count in fetch shaderChristian König
2011-03-02r600g: change the cross over point for 2d->1dDave Airlie
this fixes some rendering in the fbo-generatemipmap-formats test on my rv610. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-01r600g: add NV_conditional_render support.Dave Airlie
This is reliant on a drm patch that I posted on the list + a version bump. These will appear in drm-next today. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-01r600g: start using drm minor version to enable things.Dave Airlie
If the drm minor version is > 9 (i.e. whats in drm-next), we enable s3tc + texture tiling by default now. this changes R600_FORCE_TILING to R600_TILING which can be set to false to disable tiling on working drm. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-28r600g: truncate point sampled texture coordinatesAlex Deucher
By default the hardware rounds texcoords. However, for point sampled textures, the expected behavior is to truncate. When we have point sampled textures, set the truncate bit in the sampler. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=25871 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-28r600g: add missing evergreen INT_TO_FLT to r600_bc_get_num_operandsAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-28r600g: indentation fixesJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2011-02-28r600g: implement instanced drawing supportChristian König
2011-02-28Revert "r600g: Don't negate result of ABS instruction"Dave Airlie
This reverts commit b6d40213935da702570eca2c0861bd4b1d7f5254. This actually breaks gears here on my rv670.
2011-02-28r600g: Process TRUNC with tgis_op2Fabian Bieler
TRUNC is neither a scalar instruction nor exclusive to the Trans unit. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-28r600g: Don't negate result of ABS instructionFabian Bieler
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-25r600g: explicity set sign bits for RGTCDave Airlie
2011-02-25r600g: bc 4/5 or rgtc textures need to be tiled as well.Dave Airlie
Make the s3tc upload code more generic. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-24r600g: EXT_texture_array support.Dave Airlie
This adds EXT_texture_array support to r600g, it passes the piglit array-texture test but I suspect may not be complete. It currently requires a kernel patch to fix the CS checker to allow these, so you need to use R600_ARRAY_TEXTURE=true for now to enable them. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-23r600g: Request DWORD aligned vertex buffers.Fabian Bieler
The spec says that the offsets in the vertex-fetch instructions need to be byte-aligned and makes no specification with regard to the required alignment of the offset and stride in the vertex resource constant register. However, testing indicates that all three values need to be DWORD aligned.
2011-02-18r600g: reorganise rgtc pieces.Dave Airlie
when the cs checker fixes go upstream a lot of this can disappear into a drm version check. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-18r600g: Start a new TEX clause if the texture lookup address was fetched in ↵Fabian Bieler
the current clause Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-18r600g: Add support to dump vertex- and texture-fetch clausesFabian Bieler
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-18r600g: add BC4/5 to RGTC conversionDave Airlie
this doesn't do anything much since the rest of mesa doesn't support RGTC yet.
2011-02-17r600g: get s3tc working on cards with crappy 64/128 bit types.Dave Airlie
Some cards don't appear to work correctly with the UNORM type, so switch to the integer type, however since gallium has no integer types yet from what I can see we need to do a hack to workaround it for the blitter. Signed-off-by: Dave Airlie <airlied@redhat.com>
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