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Tested with piglit + ut2004 still seems to render okay (and it
definitely does this)
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If nvfx_framebuffer prepare and validate were called successively with
fb->zsbuf not NULL and then NULL, nvfx->hw_zeta would contain garbage and
this would cause failures in nvfx_framebuffer_relocate/OUT_RELOC(hw_zeta).
This was triggered by piglit/texwrap 2D GL_DEPTH_COMPONENT24 and caused
first a 'write to user buffer!!' error in libdrm and then worse things.
Signed-off-by: Xavier Chantry <chantry.xavier@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
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7e1bf946316ff99feaa3f2e85f70b45bd9a77ade changed
PIPE_CAP_MAX_RENDER_TARGETS to 1 on nv30.
Signed-off-by: Xavier Chantry <chantry.xavier@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
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Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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(Marek: added the initializion of "vec" in the default statement)
NOTE: This is a candidate for the 7.9 branch.
Signed-off-by: Marek Olšák <maraeo@gmail.com>
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Add explicit EVENT_TYPE field
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This fixes piglit/glsl-vs-main-return and glsl-fs-main-return for the drivers
which don't support RET (i915g, r300g, r600g, svga).
ir_to_mesa does not currently generate subroutines, but it's a matter of time
till it's added. It would then break all the drivers which don't implement
them, so this CAP makes sense.
Signed-off-by: Marek Olšák <maraeo@gmail.com>
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This fixes fdo bug 31810.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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It's intel, so always little endian!
Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
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Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
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More in line with other intel drivers.
Change to use enum by Jakob Bornecrantz.
Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
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It looks like this was meant to facilitate unfenced access to textures/
color/renderbuffers. It's totally incomplete and fundamentally broken
on a few levels:
- broken: The kernel needs to about every tiled bo to fix up bit17
swizzling on swap-in.
- unflexible: fenced/unfenced relocs from execbuffer2 do the same, much
simpler.
- unneeded: with relaxed fencing tiled gem bos are as memory-efficient
as this trick.
Hence kill it.
Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
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Somebody should find out what these are. It can be found on Windows
getting a D3DCAPS9 from IDirect3D9::GetCaps() and reading the
GuardBand* values.
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We do not know how to use more, GL_ARB_draw_buffers is not exposed on blob.
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The stride between the different clip plane registers was incorrect.
https://bugs.freedesktop.org/show_bug.cgi?id=31788
agd5f: fix evergreen as well.
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Fixes glsl-vs-point-size, although I meant to fix glsl-novertexdata.
Since swrast fails glsl-novertexdata too, I guess it's a core issue.
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Now that we have fetch shaders, the full range of VS resources
can be used for sampling.
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Makes the code much clearer.
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evergreen variant of:
9f7ec103e26c67cb077fd7d94d2fb68562b86c40
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Use fetch shader instead of having fetch instruction in the vertex
shader. Allow to restrict shader update to a smaller part when
vertex buffer input layout changes.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Fix my slot/attr confusion.
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this should at least make app use the same paths as they would for a real
driver.
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This should fix the remaining buffer alignment issues in r600g.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Vertex data swizzles are already done in the vertex shader. Doing them twice
breaks BGRA vertex arrays for example.
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RET was interpreted as END, which was wrong. Instead, if a shader contains RET
in the main function, it will fail to compile with an error message
from now on.
The hack is from early days.
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The (piglit) mipmap_limits test shows the issue very clearly.
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This driver is a fake swdri driver that perform no operations
beside allocation gallium structure and buffer for upper layer
usage.
It's purpose is to help profiling core mesa/gallium without
having pipe driver overhead hidding hot spot of core code.
scons file are likely inadequate i am unfamiliar with this
build system.
To use it simply rename is to swrast_dri.so and properly set
LIBGL_DRIVERS_PATH env variable.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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This fixes 8 texwrap format tests.
The code should handle arbitrary formats now and is cleaner.
NOTE: This is a candidate for the 7.9 branch.
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As per the ps_3_0 and vs_3_0 documentation.
The aL register in D3D9 is quite tricky to use, though.
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To match shader model 2.0 (it's impossible to fully implement ARL
with shader model 3.0 relative addressing).
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To match shader model 2.0.
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