| Age | Commit message (Collapse) | Author |
|---|
|
This prevents vertex shaders from referencing invalid memory locations when
the shader is operating on less than four vertices or fragments.
|
|
|
|
|
|
|
|
TGSI shaders are translated into SPE instructions which are then sent to
the SPEs for execution. Only a few opcodes work, no swizzling yet, no
support for constants/immediates, etc.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Do code generation for alpha test, z test, stencil, blend, colormask
and framebuffer/tile read/write as a single code block.
Ian's previous blend/z/stencil test code is still there but mostly disabled
and will be removed soon.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
softpipe.
We want to make it env variable, or even better, autodetect as the feature makes
softpipe run slower on a single CPU.
|
|
Store only input and inout of a quad_header in job que.
|
|
parts.
|
|
Use condition vars to communicate between threads instead of stalling.
|
|
Configured for 2 cores.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Options so far:
"checker" module tile clear color by SPU ID to see where the tiles are
"sync" to do synchronous DMA (only partially implemented)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
