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Seems to be the only way to stay fully portable.
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Conflicts:
configs/default
src/gallium/auxiliary/pipebuffer/pb_buffer_fenced.c
src/mesa/main/version.h
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This patch removes PIPE_TEX_FILTER_ANISO.
Anisotropic filtering is enabled if and only if max_anisotropy > 1.0.
Values between 0.0 and 1.0, inclusive, of max_anisotropy are to be
considered equivalent, and meaning to turn off anisotropic filtering.
This approach has the small drawback of eliminating the possibility of
enabling anisotropic filter on either minification or magnification
separately, which Radeon hardware seems to support, is currently
support by Gallium but not exposed to OpenGL. If this is actually
useful it could be handled by splitting max_anisotropy in two values
and adding an appropriate OpenGL extension.
NOTE: some fiddling & reformatting by keithw to get this patch to
apply. Hopefully nothing broken in the process.
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Invalid assertion found by Roel Kluin <roel.kluin@gmail.com>
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- The previous solution was hacky and didn't do subchannel autobinding.
- The beheaviour should match what libdrm_nouveau does closely.
- The solution remains statically sized, but when debugging is on it will check
for abuse.
Signed-off-by: Maarten Maathuis <madman2003@gmail.com>
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- This avoids problematic "reloc'ed while mapped" messages and
some associated corruption as well.
Signed-off-by: Maarten Maathuis <madman2003@gmail.com>
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To ensure that a new result that happens to have the same address
of the old one will be detected as a change.
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Even shader ID doesn't change. Otherwise the token change is not
effective.
This reverts regression from commit
cdb445f3a9285e2d8f042a07021ade78b94e0156. Regression could be seen in
Quake3's loading screen -- the upper right corner of the screen would
be black.
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Conflicts:
src/gallium/drivers/identity/id_context.c
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This is to differentiate it from its unsigned version, TGSI_OPCODE_USHR.
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Conflicts:
docs/relnotes.html
src/gallium/drivers/llvmpipe/lp_tex_sample_c.c
src/gallium/drivers/r300/r300_cs.h
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
src/mesa/main/enums.c
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Make it easier to insert/remove error branches.
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The abscense was being masked previously.
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Makes integration of gallium into out of tree components much easier. No
pratical change for components in this tree,
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Conflicts:
configs/darwin
src/gallium/auxiliary/util/u_clear.h
src/gallium/state_trackers/xorg/xorg_exa_tgsi.c
src/mesa/drivers/dri/i965/brw_draw_upload.c
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The immediate's bits eat the condition bits.
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Cannot change hw reg assigned to a TGSI TEMP on the fly if
we are in a loop, conditional, or can jump around wildly.
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Not that they make much sense on nv50, but we also do LIT ...
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If we create multiple instances of an nv50_reg referencing
them same resource, register allocation from alloc_reg has
to be done with the original nv50_reg.
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Also fixes RSQ of negative sources.
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This negation would only be triggered in situations
where it's incorrect.
The caller of set_immd should negate the immediate value
in the instruction itself if desired, and will also know
if it's a float or an int.
ADD TEMP[0], CONST[0], -IMMD[0] would load the immediate
into extra TEMP, negated, and set the negate flag in add
as well - double negation.
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Currently in nvXX_transfer_new a temporary as large as the surface is created.
If the subrectangle is not the whole texture we would need to read
back the whole texture, but we aren't.
Thus, everything but the subrectangle specified is loaded as garbage.
This can be seen in progs/demos/ray.
This patch fixes the problem by creating a temporary that covers only
the desired subrectangle.
That makes us hit an alignment assert in nv04_surface_2d.c. Fix it
using the point registers instead of manipulating the swizzled surface
offset to account for the destination coordinates (which do not seem
to have a 1024 limit).
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
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- unreference state objects so that buffer objects are unreferenced and
eventually destroyed
- free channel at screen's destruction
Based on Krzysztof Smiechowicz's patch.
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nVidia hardware seems to swizzle rectangular texture (with width !=
height) coordinates by swizzling the lower bits and then adding the
higher bits from the larger dimension.
However, nv04_swizzle_bits ignores width and height and just
interleaves everything.
This causes problems with rectangular POT textures with height or
width 2048 or 4096 (but not 2048x1024 where it works by chance) since
the driver swizzles them in 1024x1024 chunks and gets the start
position for the non-first chunks wrong.
The following patch seems to fix those problems.
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I just coded a patch that does this and seems to work fine. It must be
fixed since it breaks OpenGL (or the state tracker can be changed, but
it seems better to do it in the driver).
The patch also fixes NV20 and NV30 in the same way. They compile but
are untested.
I would guess that using the 3D engine is faster for the larger
levels, but the 2D engine is faster for the smaller ones (and lacks
this issue).
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CMP and SCS can produce incorrect results if the source and
destination are the same.
This patch should fix the issues.
CMP is fixed by predicating both moves.
SCS by changing the order if the source component is X.
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Not since 6094e79f4e3350d123c7532b1c73faa60834a62d.
Drivers now need to flush draw module explicitely (which explains why
all those previous commits adding draw_flushes calls were necessary).
This is a good thing, but it's tricky to get this right in face of user buffers
(it's not even clear who has the responsibility to flush when a user buffer
is seen -- statetracker or pipe driver), so just force flush (temporarily)
since it's not a bottleneck now.
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