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With this fix, the glsl/brick demo runs.
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Conflicts:
src/gallium/auxiliary/gallivm/instructionssoa.cpp
src/gallium/auxiliary/gallivm/soabuiltins.c
src/gallium/auxiliary/rtasm/rtasm_x86sse.c
src/gallium/auxiliary/rtasm/rtasm_x86sse.h
src/mesa/main/texenvprogram.c
src/mesa/shader/arbprogparse.c
src/mesa/shader/prog_statevars.c
src/mesa/state_tracker/st_draw.c
src/mesa/vbo/vbo_exec_draw.c
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Lots of restrictions for now (one 2D texture, no mipmaps, etc.) for now
but basic texture demos work.
TEX, TXD, TXP do the same thing for the time being.
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Used for SIN, COS, EXP2, LOG2, POW instructions. TEX next.
Fixed some bugs in MIN, MAX, DP3, DP4, DPH instructions.
In rtasm code:
Special-case spe_lqd(), spe_stqd() functions so they take byte offsets but
low-order 4 bits are shifted out. This makes things consistant with SPU
assembly language conventions.
Added spe_get_registers_used() function.
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Besides meaning x86 and x86-64 architecture, it also depends on SSE2
support enabled on gcc.
This fixes the linux-debug build.
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This set of code changes are for stencil code generation
support. Both one-sided and two-sided stenciling are supported.
In addition to the raw code generation changes, these changes had
to be made elsewhere in the system:
- Added new "register set" feature to the SPE assembly generation.
A "register set" is a way to allocate multiple registers and free
them all at the same time, delegating register allocation management
to the spe_function unit. It's quite useful in complex register
allocation schemes (like stenciling).
- Added and improved SPE macro calculations.
These are operations between registers and unsigned integer
immediates. In many cases, the calculation can be performed
with a single instruction; the macros will generate the
single instruction if possible, or generate a register load
and register-to-register operation if not. These macro
functions are: spe_load_uint() (which has new ways to
load a value in a single instruction), spe_and_uint(),
spe_xor_uint(), spe_compare_equal_uint(), and spe_compare_greater_uint().
- Added facing to fragment generation. While rendering, the rasterizer
needs to be able to determine front- and back-facing fragments, in order
to correctly apply two-sided stencil. That requires these changes:
- Added front_winding field to the cell_command_render block, so that
the state tracker could communicate to the rasterizer what it
considered to be the front-facing direction.
- Added fragment facing as an input to the fragment function.
- Calculated facing is passed during emit_quad().
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Simple function call works now, but we don't save/restore the caller's registers yet.
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Will be used for instructions like SIN/COS/POW/TEX/etc. The PPU needs to
know the address of some functions in the SPU address space. Send that
info to the PPU/main memory rather than patch up shaders on the SPU side.
Not finished/tested yet...
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The colormask code generation had assumed that its input packed pixels were
in RGBA format. In fact, the format they're in is dependent on the
pipe color format.
Now the color format is passed in to gen_colormask(), and proper
color format-dependent SPU code is generated.
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for TGSI instructions. The logic should operate on the origin channel not the swizzled channel.
Please enter the commit message for your changes.
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softpipe. Optimized FLR and FRC. Fixed writeback logic for DP3, DP4 and DPH.
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32-byte boundary
To make sure even/odd instructions hit the right pipes.
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softpipe: MOV, ADD, MUL, SGE, SUB, MAD, ABS, SLT, MIN, MAX, LRP, DP3, DP4, CMP, FLR
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Also: improve float/int Z conversion.
Use clgt instead of cgt in depth test since we're comparing unsigned values.
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cmd_state_fragment_ops() was inverted
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- rtasm_ppc_spe.c, rtasm_ppc_spe.h: added a new macro function
"spe_load_uint" for loading and splatting unsigned integers
in a register; it will use "ila" for values 18 bits or less,
"ilh" for word values that are symmetric across halfwords,
"ilhu" for values that have zeroes in their bottom halfwords,
or "ilhu" followed by "iohl" for general 32-bit values.
Of the 15 color masks of interest, 4 are 18 bits or less,
2 are symmetric across halfwords, 3 are zero in the bottom
halfword, and 6 require two instructions to load.
- cell_gen_fragment.c: added full codegen for logic op and
color mask.
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progs/demos: added new demo "fbo_firecube"
progs/glsl: added new demo "pointcoord"
src/gallium/drivers/cell/spu: added the g3d_spu executable, a Cell SPU
executable file, which seems to be occasionally built as part of the
cell driver
src/glu/sgi: added "exptmp", a byproduct of the "mklib" process that
sometimes gets deleted and sometimes not.
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Conflicts:
src/mesa/shader/slang/slang_link.c
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