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This is reliant on a drm patch that I posted on the list + a version bump.
These will appear in drm-next today.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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the context init is separate for these gpus.
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This avoid any issue when context is free and we still try to
access fence through radeon structure.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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this code was pretty much duplicated, thanks to Henri Verbeet on irc for
pointing it out.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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r600g is up to a point where all small CPU cycle matter and pb* turn
high on profile. It's mostly because pb try to be generic and thus
trigger unecessary check for r600g driver. To avoid having too much
abstraction & too much depth in the call embedded everythings into
r600_bo. Make code simpler & faster. The performance win highly depend
on the CPU & application considered being more important on slower CPU
and marginal/unoticeable on faster one.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Add explicit EVENT_TYPE field
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Use fetch shader instead of having fetch instruction in the vertex
shader. Allow to restrict shader update to a smaller part when
vertex buffer input layout changes.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Avoid having object ending up in dead list of dirty object.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Got a speed up by tracking the dirty blocks in a seperate list instead of looping through all blocks. This version should work with block that get their dirty state disabled again and I added a dirty check during the flush as some blocks were already dirty.
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Flush read cache before writting register. Track flushing inside
of a same cs and avoid reflushing same bo if not necessary. Allmost
properly force flush if bo rendered too and then use as a texture
in same cs (missing pipeline flush dunno if it's needed or not).
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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since we plan on using dx10 constant buffers everywhere.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Add bo offset everywhere needed if r600_bo is ever a sub bo
of a bigger bo.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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this sets up a single loop constant like r600c does.
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just a typo in the register headers.
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this gets rid of lots of the instability on evergreen,
which isn't surprising since it really broken not to flush caches.
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we'll need this for color tiling on evergreen.
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These need to be emitted, we also need them to do proper vtx start,
instead of abusing index offset.
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This avoid to overcount the number of dwords we need and
thus avoid maximazation of cs buffer use.
Signed-off-by: Jerome Glisse <jglisse@redhat.com
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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