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path: root/src/gallium/winsys/r600
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2010-09-29r600g: cleanupJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-29r600g: delete old pathJerome Glisse
Lot of clean can now happen. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-29r600g: use a hash table instead of groupJerome Glisse
Instead of creating group of register use a hash table to lookup into which block each register belongs. This simplify code a bit. Signed-off-by: Jerome Glisse <jglisse@redhat.com
2010-09-29r600g: move radeon.h members around to add back map flushing.Dave Airlie
2010-09-28r600g: suspend/resume occlusion query around clear/copyJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-27r600g: fix occlusion query after change to block structureJerome Glisse
block->reg point to register value not block->pm4 which point to packet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-27r600g: fix pointsprite & resource unbindingJerome Glisse
When asking to bind NULL resource assume it's unbinding so free resource and unreference assoicated buffer. Also fix pointsprite parameter. Fix glsl-fs-pointcoord & fp-fragment-position Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-27r600g: build packet header onceJerome Glisse
Build packet header once and allow to add fake register support so we can handle things like indexed set of register (evergreen sampler border registers for instance. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-27r600g: add evergreen texture resource properly.Dave Airlie
adding sampler border looks impossible with current design, another day, another corner case not worked out.
2010-09-26r600g: disable early cull optimization when occlusion query runningJerome Glisse
When occlusion query are running we want to have accurate fragment count thus disable any early culling optimization GPU has. Based on work from Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-26r600g: Include p_compiler.h instead of malloc.h.Vinson Lee
2010-09-26r600g: Remove unused variables.Vinson Lee
Fixes these GCC warnings. radeon.c: In function 'radeon_new': radeon.c:59: warning: unused variable 'k' radeon.c:59: warning: unused variable 'j' radeon.c:59: warning: unused variable 'id' radeon.c:59: warning: unused variable 'i'
2010-09-26r600g: Don't return a value in function returning void.Vinson Lee
Fixes this GCC warning. radeon_state.c: In function 'radeon_state_fini': radeon_state.c:140: warning: 'return' with a value, in function returning void
2010-09-25r600g: Remove unused variable.Vinson Lee
Fixes this GCC warning. radeon_bo_pb.c: In function 'radeon_bo_pb_create_buffer': radeon_bo_pb.c:178: warning: unused variable 'domain'
2010-09-25r600g: add eg db count control register.Dave Airlie
2010-09-24r600g: bring over fix from old path to new pathJerome Glisse
Up to 2010-09-19: r600g: fix tiling support for ddx supplied buffers 9b146eae2521d8e5f6d3cbefa4f6f7737666313a user buffer seems to be broken... new to fix that. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-24r600g: fix evergreen new pathJerome Glisse
glxgears seems to work, had somelockup but now they seems to have vanish. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-24r600g: fix evergreen new pathJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-24r600g: evergreen fix for new designJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-24r600g: move use_mem_constants flags for new designs structure alignmentJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-24r600g: fix typo in evergreen define (resource are in [0x30000;0x34000] range)Jerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-23r600g: initial evergreen support in new pathJerome Glisse
This doesn't work yet. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-23r600g: fix typo in evergreen register listDave Airlie
pointed out by glisse on irc.
2010-09-22r600g: disable shader rebuild optimization & account cb flush packetJerome Glisse
Shader rebuild should be more clever, we should store along each shader all the value that change shader program rather than using flags in context (ie change sequence like : change vs buffer, draw, change vs buffer, switch shader will trigger useless shader rebuild). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-22r600g: flush color buffer after draw commandJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-21r600g: occlusion query for new designJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-21r600g: directly allocate bo for user bufferJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-21r600g: fix eg texture borders.Dave Airlie
texture border regs are indexed on evergreen.
2010-09-20r600g: add back reference check when mapping bufferJerome Glisse
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-20r600g: use pipe context for flushing inside mapJerome Glisse
This allow to share code path btw old & new, also remove check on reference this might make things a little slower but new design doesn't use reference stuff. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-20r600g: move chip class to radeon common structureJerome Glisse
So texture code can be shared btw new state design & old one. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-20r600g: only flush for the correct colorbuffer, not all of them.Dave Airlie
2010-09-20r600g: fixup r700 CB_SHADER_CONTROL register.Dave Airlie
r600c emits this with a mask of each written output.
2010-09-20r600g: fix tiling support for ddx supplied buffersDave Airlie
needed to emit some more relocs to the kernel.
2010-09-20r600g: send correct surface base update for multi-cbufsDave Airlie
2010-09-19r600g: Respect PB_USAGE_UNSYNCHRONIZED in radeon_bo_pb_map_internal().Henri Verbeet
2010-09-19r600g: Buffer object maps imply a wait.Henri Verbeet
Unless e.g. PB_USAGE_DONTBLOCK or PB_USAGE_UNSYNCHRONIZED would be specified.
2010-09-19r600g: Check for other references before checking for existing mappings in ↵Henri Verbeet
radeon_bo_pb_map_internal(). Having a non-NULL data pointer doesn't imply it's safe to reuse that mapping, it may have been unmapped but not flushed yet.
2010-09-17r600g: Silence uninitialized variable warning.Vinson Lee
2010-09-17r600g: Fix memory leak on error path.Vinson Lee
2010-09-17r600g: Fix implicit declaration warning.Vinson Lee
Fixes this GCC warning. r600_state2.c: In function 'r600_context_flush': r600_state2.c:946: error: implicit declaration of function 'drmCommandWriteRead'
2010-09-17r600g: Remove unnecessary headers.Vinson Lee
2010-09-17r600g: alternative command stream building from contextJerome Glisse
Winsys context build a list of register block a register block is a set of consecutive register that will be emited together in the same pm4 packet (the various r600_block* are there to provide basic grouping that try to take advantage of states that are linked together) Some consecutive register are emited each in a different block, for instance the various cb[0-7]_base. At winsys context creation, the list of block is created & an index into the list of block. So to find into which block a register is in you simply use the register offset and lookup the block index. Block are grouped together into group which are the various pkt3 group of config, context, resource, Pipe state build a list of register each state want to modify, beside register value it also give a register mask so only subpart of a register can be updated by a given pipe state (the oring is in the winsys) There is no prebuild register list or define for each pipe state. Once pipe state are built they are bound to the winsys context. Each of this functions will go through the list of register and will find into which block each reg falls and will update the value of the block with proper masking (vs/ps resource/constant are specialized variant with somewhat limited capabilities). Each block modified by r600_context_pipe_state_set* is marked as dirty and we update a count of dwords needed to emit all dirty state so far. r600_context_pipe_state_set* should be call only when pipe context change some of the state (thus when pipe bind state or set state) Then to draw primitive you make a call to r600_context_draw void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw) It will check if there is enough dwords in current cs buffer and if not will flush. Once there is enough room it will copy packet from dirty block and then add the draw packet3 to initiate the draw. The flush will send the current cs, reset the count of dwords to 0 and remark all states that are enabled as dirty and recompute the number of dwords needed to send the current context. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-18r600g: oops got the use_mem_constant the wrong way around.Dave Airlie
this fixes evergreen gears again.
2010-09-17r600g: use calloc for ctx bo allocationsDave Airlie
since the reference code relies on these being NULL.
2010-09-17r600g: fixup map flushing.Dave Airlie
long lived maps were getting removed when they shouldn't this tries to avoid that problem by only adding to the flush list on unmap.
2010-09-17r600g: add winsys bo caching.Dave Airlie
this adds the bo caching layer and uses it for vertex/index/constant bos. ctx needs to take references on hw bos so the flushing works okay, also needs to flush the maps.
2010-09-17r600g: add support for kernel boDave Airlie
this moves to using a pb bufmgr instead of kernel bos directly.
2010-09-17r600g: use malloc bufmgr for constant buffersDave Airlie
2010-09-17r600g: move constant buffer creation behind winsys abstraction.Dave Airlie
this paves the way for moving to pb bufmgrs now.
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