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These were previously being left in the default (D3D) mode. This mean
that triangles were drawn slightly incorrectly, but also because this
state is relied on by the u_blitter code, all blits were half a pixel
off.
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This opens the question of what interface the winsys layer should
really have for talking about these concepts.
For now I'm using the existing gallium resource usage concept, but
there is no reason not use terms closer to what the hardware
understands - eg. the domains themselves.
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Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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That way assert(map_count >= 0) can actually fail when we screwed up.
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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This ensures that we increase bo->map_count when radeon_bo_map_internal()
returns successfully, which in turn makes sure we don't decrement
bo->map_count below zero later.
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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Use scons target and dependency system instead of ad-hoc options.
Now is simply a matter of naming what to build. For example:
scons libgl-xlib
scons libgl-gdi
scons graw-progs
scons llvmpipe
and so on. And there is also the possibility of scepcified subdirs, e.g.
scons src/gallium/drivers
If nothing is specified then everything will be build.
There might be some rough corners over the next days. Please bare with me.
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radeon_bo_destroy() will want to read the list field. Without this patch,
we'd end up evaluating the list pointers before they have been properly
set up when we destroyed the newly created bo if it cannot be mapped.
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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Move away from the old Mesa-oriented names.
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Fixes a crash upon exit when using remote display.
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we need to know if the back is tiled so we can blit from it properly.
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Would try to destroy radeon->cman, radeon->kman both which were still
NULL.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Avoid having object ending up in dead list of dirty object.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Since flush rework there could be only one relocation per
register in a block.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Got a speed up by tracking the dirty blocks in a seperate list instead of looping through all blocks. This version should work with block that get their dirty state disabled again and I added a dirty check during the flush as some blocks were already dirty.
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Flush read cache before writting register. Track flushing inside
of a same cs and avoid reflushing same bo if not necessary. Allmost
properly force flush if bo rendered too and then use as a texture
in same cs (missing pipeline flush dunno if it's needed or not).
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Allow fast lookup of relocation information & id which
was a CPU time consumming operation.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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if we know the bo has gone not busy, no need to add another bo wait
thanks to Andre (taiu) on irc for pointing this out.
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since we plan on using dx10 constant buffers everywhere.
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we don't use this since constant buffers are now being used on all gpus.
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When we go to do a lot of bos in one draw like constant bufs we need
to avoid bouncing off the busy ioctl, this mitigates by backing off
on busy bos for a short amount of times.
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this just keeps a list of bos submitted together, and uses them to decide
bo busy state for the whole group.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Add bo offset everywhere needed if r600_bo is ever a sub bo
of a bigger bo.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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no wonder it was slow, the code is deliberately forcing stuff into GTT,
we used to have domain management but it seems to have disappeared.
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this function was taking quite a lot of pointless CPU.
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this sets up a single loop constant like r600c does.
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just a typo in the register headers.
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this gets rid of lots of the instability on evergreen,
which isn't surprising since it really broken not to flush caches.
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we'll need this for color tiling on evergreen.
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