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A cleaner solution would be preferable, but this does no harm and works.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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texture border regs are indexed on evergreen.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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This allow to share code path btw old & new, also
remove check on reference this might make things
a little slower but new design doesn't use reference
stuff.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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So texture code can be shared btw new state design
& old one.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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r600c emits this with a mask of each written output.
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needed to emit some more relocs to the kernel.
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Unless e.g. PB_USAGE_DONTBLOCK or PB_USAGE_UNSYNCHRONIZED would be specified.
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radeon_bo_pb_map_internal().
Having a non-NULL data pointer doesn't imply it's safe to reuse that mapping,
it may have been unmapped but not flushed yet.
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Fixes this GCC warning.
r600_state2.c: In function 'r600_context_flush':
r600_state2.c:946: error: implicit declaration of function 'drmCommandWriteRead'
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Winsys context build a list of register block a register block is
a set of consecutive register that will be emited together in the
same pm4 packet (the various r600_block* are there to provide basic
grouping that try to take advantage of states that are linked together)
Some consecutive register are emited each in a different block,
for instance the various cb[0-7]_base. At winsys context creation,
the list of block is created & an index into the list of block. So
to find into which block a register is in you simply use the register
offset and lookup the block index. Block are grouped together into
group which are the various pkt3 group of config, context, resource,
Pipe state build a list of register each state want to modify,
beside register value it also give a register mask so only subpart
of a register can be updated by a given pipe state (the oring is
in the winsys) There is no prebuild register list or define for
each pipe state. Once pipe state are built they are bound to
the winsys context.
Each of this functions will go through the list of register and
will find into which block each reg falls and will update the
value of the block with proper masking (vs/ps resource/constant
are specialized variant with somewhat limited capabilities).
Each block modified by r600_context_pipe_state_set* is marked as
dirty and we update a count of dwords needed to emit all dirty
state so far.
r600_context_pipe_state_set* should be call only when pipe context
change some of the state (thus when pipe bind state or set state)
Then to draw primitive you make a call to r600_context_draw
void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw)
It will check if there is enough dwords in current cs buffer and
if not will flush. Once there is enough room it will copy packet
from dirty block and then add the draw packet3 to initiate the draw.
The flush will send the current cs, reset the count of dwords to
0 and remark all states that are enabled as dirty and recompute
the number of dwords needed to send the current context.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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this fixes evergreen gears again.
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since the reference code relies on these being NULL.
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long lived maps were getting removed when they shouldn't this
tries to avoid that problem by only adding to the flush list
on unmap.
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this adds the bo caching layer and uses it for vertex/index/constant bos.
ctx needs to take references on hw bos so the flushing works okay, also
needs to flush the maps.
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this moves to using a pb bufmgr instead of kernel bos directly.
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this paves the way for moving to pb bufmgrs now.
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introduce an abstraction layer between kernel bos and the winsys BOs.
this is to allow plugging in pb manager with minimal disruption to pipe driver.
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no need for this info to be exported to pipe driver.
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caused by 0b9eb5c9bb03e5134d9a41786178100109e80c5a
test run glxgears, resize.
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This fixes a DRM deadlock in the cubestorm xscreensaver, because somehow
there must not be 2 different BOs relocated in one CS if both BOs back
the same handle. I was told it is impossible to happen, but apparently
it is not, or there is something else wrong.
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https://bugs.freedesktop.org/show_bug.cgi?id=30145
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If the buffer we are attempting to map is referenced by the unsubmitted
command stream for this context, we need to flush the command stream,
however to do that we need to be able to access the context at the lowest
level map function, currently we set the buffer in the toplevel map, but this
racy between context. (we probably have a lot more issues than that.)
I'll look into a proper solution as suggested by jrfonseca when I get some time.
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Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
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for evergreen I ended up using a non-contig array of states, but
this code needs a bit of fixing up to deal with that.
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adds shader opcodes + assembler support (except ARL)
uses constant buffers
add interp instructions in fragment shader
adds all evergreen hw states
adds evergreen pm4 support.
this runs gears for me on my evergreen
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the DDX and r600c both flush cb/db after the draw is emitted,
as long as they do that, r600g can't be different, as it races.
We end up with r600g flush, set CB, DDX set CB, flush. This
was causing misrendering on my evergreen, where sometimes the drawing
would go to an old CB.
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the code should reloc correctly a single BO 3 times.
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DX9 constants were in the constant file, and evergreen no longer support
cfile. r600/700 can also use constants in memory buffers, so add the code
(disabled for now) to enable that as precursor for evergreen.
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This was inherently fragile as any changes to r600_states.h would also
need manual updating of all of the bits in radeon.h. Just add a simple
python script to do the conversion, its not hooked up to make at all.
This also will make adding evergreen a bit easier.
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Previously bind sampler/sampler_view can be converted and endup
overwritting the current state we want to schedule. Example :
bind texA texB to sampler_view[0] & sampler_view[1], render,
bind texB to sampler_view[0] render. Now state associated to
texB are set to configure sampler_view slot 0, but as we don't
unbind sampler_view[1] still point to texB state so we end up
with sampler_view[1] overwritting sampler_view[0], which gives
wrong rendering if next rendering bind texA to sampler_view[0],
it will endup as texB is bound to sampler_view[0]. If you are
not confuse at that point give me a call i will be buying you
beer.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Make state statically allocated, this kills a bunch of code
and avoid intensive use of malloc/free. There is still a lot
of useless duplicate function wrapping that can be kill. This
doesn't improve yet performance, needs to avoid memcpy states
in radeon_ctx_set_draw and to avoid rebuilding vs_resources,
dsa, scissor, cb_cntl, ... states at each draw command.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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This reverts commit 1fa7245c348cb7aced81f1672140f64cb6450e2f.
Conflicts:
src/gallium/drivers/r600/r600_state.c
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This reverts commit de0b76cab22caa9fc7260f80acb8f151ccced6c5, its pre-computes the texture state wrong,
you can't just use an array of levels, since you can have FBOs to depth texture slices inside a level as well
it would get really messy quickly. Probably need to split commits like this up into pieces for each piece
of state, so we can revert bits easier in case of regressions.
This also break 5 piglit tests, and valgrind starts to warn about invalid read/writes after this.
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Idea is to build hw state at pipe state creation and
reuse them while keeping a non PM4 packet interface
btw winsys & pipe driver. This commit also force rebuild
of pm4 packet on each call to radeon_state_pm4 which
in turn slow down everythings, this will be addressed.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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