Age | Commit message (Collapse) | Author |
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this sets up a single loop constant like r600c does.
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just a typo in the register headers.
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this gets rid of lots of the instability on evergreen,
which isn't surprising since it really broken not to flush caches.
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we'll need this for color tiling on evergreen.
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These need to be emitted, we also need them to do proper vtx start,
instead of abusing index offset.
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Save a lot of call into the kernel and thus improve performances.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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This avoid to overcount the number of dwords we need and
thus avoid maximazation of cs buffer use.
Signed-off-by: Jerome Glisse <jglisse@redhat.com
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Remove duplicated include.
Signed-off-by: Brian Paul <brianp@vmware.com>
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mainly remove 2 suffix from function names
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Fixes SCons build.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Lot of clean can now happen.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Instead of creating group of register use a hash table
to lookup into which block each register belongs. This
simplify code a bit.
Signed-off-by: Jerome Glisse <jglisse@redhat.com
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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block->reg point to register value not block->pm4 which point
to packet.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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When asking to bind NULL resource assume it's unbinding
so free resource and unreference assoicated buffer.
Also fix pointsprite parameter.
Fix glsl-fs-pointcoord & fp-fragment-position
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Build packet header once and allow to add fake register support so
we can handle things like indexed set of register (evergreen sampler
border registers for instance.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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adding sampler border looks impossible with current design, another day, another corner case not worked out.
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When occlusion query are running we want to have accurate
fragment count thus disable any early culling optimization
GPU has.
Based on work from Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Fixes these GCC warnings.
radeon.c: In function 'radeon_new':
radeon.c:59: warning: unused variable 'k'
radeon.c:59: warning: unused variable 'j'
radeon.c:59: warning: unused variable 'id'
radeon.c:59: warning: unused variable 'i'
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Fixes this GCC warning.
radeon_state.c: In function 'radeon_state_fini':
radeon_state.c:140: warning: 'return' with a value, in function returning void
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Fixes this GCC warning.
radeon_bo_pb.c: In function 'radeon_bo_pb_create_buffer':
radeon_bo_pb.c:178: warning: unused variable 'domain'
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Up to 2010-09-19:
r600g: fix tiling support for ddx supplied buffers
9b146eae2521d8e5f6d3cbefa4f6f7737666313a
user buffer seems to be broken... new to fix that.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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glxgears seems to work, had somelockup but now they seems to have vanish.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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NOTE: This is a candidate for the 7.9 branch.
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Based on commit 3ddc714b20ac4e28b80c6f88d1993445fff2262c by Dave Airlie.
NOTE: This is a candidate for the 7.9 branch.
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This doesn't work yet.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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pointed out by glisse on irc.
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Shader rebuild should be more clever, we should store along each
shader all the value that change shader program rather than using
flags in context (ie change sequence like : change vs buffer, draw,
change vs buffer, switch shader will trigger useless shader rebuild).
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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A cleaner solution would be preferable, but this does no harm and works.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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texture border regs are indexed on evergreen.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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