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2010-09-19r600g: Use align() instead of handrolled code.Corbin Simpson
2010-09-20r600g: drop debugging that snuck inDave Airlie
2010-09-20r600g: clean up valgrind issues on maxtargets test.Dave Airlie
2010-09-20r600g: fix fbo-drawbuffers-maxtargetsDave Airlie
we were leaking buffers since the flush code was added, it wasn't dropping references. move setting up flush to the set_framebuffer_state. clean up the flush state object. make more space in the BOs array for flushing.
2010-09-20r600g: send correct surface base update for multi-cbufsDave Airlie
2010-09-20r600g: modify index buffers for sizes the hw can't deal with.Dave Airlie
this just uses the common code from r300g now in util to do translations on r600g.
2010-09-20util/r300g: split the r300 index buffer modifier functions out to utilDave Airlie
These can be used by other drivers, like r600g. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-09-20r600g: fix exports_ps to export a number not a mask.Henri Verbeet
2010-09-20scons: Link against talloc in the Gallium DRI driversJakob Bornecrantz
2010-09-20rbug: Add function to get opcode name stringJakob Bornecrantz
2010-09-20rbug: Cast opcode to corrent int sizeJakob Bornecrantz
2010-09-19Revert "r600g: Flush upload buffers before draws instead of before flushes."Henri Verbeet
This reverts commit a1d9a58b825825723f1c5f7705f2ed3ef834038a. Flushing the upload buffers on draw is wrong, uploads aren't supposed to cause flushes in the first place. The real issue was radeon_bo_pb_map_internal() not respecting PB_USAGE_UNSYNCHRONIZED.
2010-09-19r600g: Respect PB_USAGE_UNSYNCHRONIZED in radeon_bo_pb_map_internal().Henri Verbeet
2010-09-19gallium/docs: Fixed a typo in the SCS opcode description.Tilman Sauerbeck
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
2010-09-19auxiliary: fix depth-only and stencil-only clearsLuca Barbieri
Depth-only and stencil-only clears should mask out depth/stencil from the output, mask out stencil/input from input, and OR or ADD them together. However, due to a typo they were being ANDed, resulting in zeroing the buffer.
2010-09-19r600g: Buffer object maps imply a wait.Henri Verbeet
Unless e.g. PB_USAGE_DONTBLOCK or PB_USAGE_UNSYNCHRONIZED would be specified.
2010-09-19r600g: Remove a redundant flush in r600_texture_transfer_map().Henri Verbeet
radeon_ws_bo_map() will already take care of that if needed.
2010-09-19r600g: Check for other references before checking for existing mappings in ↵Henri Verbeet
radeon_bo_pb_map_internal(). Having a non-NULL data pointer doesn't imply it's safe to reuse that mapping, it may have been unmapped but not flushed yet.
2010-09-19r600g: Flush upload buffers before draws instead of before flushes.Henri Verbeet
If a upload buffer is used by a previous draw that's still in the CS, accessing it would need a context flush. However, doing a context flush when mapping the upload buffer would then flush/destroy the same buffer we're trying to map there. Flushing the upload buffers before a draw avoids both the CS flush and the upload buffer going away while it's being used. Note that u_upload_data() could e.g. use a pool of buffers instead of allocating new ones all the time if that turns out to be a significant issue.
2010-09-19st/egl: s/kms/drm/ on the drm backend.Chia-I Wu
s/kms/drm/, s/kdpy/drmdpy/, and so forth.
2010-09-19st/egl: Rename kms backend to drm.Chia-I Wu
The main use of the backend is to support EGL_MESA_drm_display. drm should be a better name.
2010-09-19st/egl: Split modeset code support to modeset.c.Chia-I Wu
The modeset code supports now obsolete EGL_MESA_screen_surface. Move it to a file of its own.
2010-09-19r600g: only emit uses waterfall on r6xx hw.Dave Airlie
2010-09-19r600g; add uses waterfall to asm cf for r6xx.Dave Airlie
On r6xx if an MOVA instruction is emitted we should set this bit.
2010-09-19r600g: Added support for TGSI_SEMANTIC_FACE.Tilman Sauerbeck
This makes the 'glsl1-gl_FrontFacing var (1)' piglit test pass. Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
2010-09-18nv50: Remove dead initialization.Vinson Lee
2010-09-18nv50: Remove dead initialization.Vinson Lee
2010-09-18nv50: Silence missing initializer warning.Vinson Lee
Fixes this GCC warning. nv50_state_validate.c:336: warning: missing initializer nv50_state_validate.c:336: error: (near initialization for 'validate_list[20].func')
2010-09-18nv50: fix typo in fifo packet length limitChristoph Bumiller
2010-09-18nv50: emit constbuf relocs before uploading constantsChristoph Bumiller
2010-09-18nv50: add relocs for stack and local mem buffersChristoph Bumiller
2010-09-18r600g: Remove unused variable.Vinson Lee
2010-09-18nvfx: Silence uninitialized variable warnings.Vinson Lee
2010-09-18nvfx: Remove const qualifer from nvfx_vertprog_translate.Vinson Lee
Silences this GCC warning. nvfx_vertprog.c: In function 'nvfx_vertprog_translate': nvfx_vertprog.c:998: warning: assignment discards qualifiers from pointer target type
2010-09-17r600g: Silence unused variable warnings.Vinson Lee
The variables are used in code that is currently ifdef'ed out.
2010-09-17r600g: Silence uninitialized variable warning.Vinson Lee
2010-09-17r600g: Fix memory leak on error path.Vinson Lee
2010-09-17r600g: Fix implicit declaration warning.Vinson Lee
Fixes this GCC warning. r600_state2.c: In function 'r600_context_flush': r600_state2.c:946: error: implicit declaration of function 'drmCommandWriteRead'
2010-09-17r600g: Remove unnecessary headers.Vinson Lee
2010-09-17r600g: Remove unnecessary header.Vinson Lee
2010-09-17llvmpipe: Default to no threading on single processor systems.José Fonseca
2010-09-17util: linearized sRGB values don't fit into 8bitsJosé Fonseca
Fixes glean texture_srgb test.
2010-09-17gallivm: added missing case for PIPE_TEXTURE_RECTBrian Paul
Fixes fd.o bug 30245
2010-09-17r600g: alternative command stream building from contextJerome Glisse
Winsys context build a list of register block a register block is a set of consecutive register that will be emited together in the same pm4 packet (the various r600_block* are there to provide basic grouping that try to take advantage of states that are linked together) Some consecutive register are emited each in a different block, for instance the various cb[0-7]_base. At winsys context creation, the list of block is created & an index into the list of block. So to find into which block a register is in you simply use the register offset and lookup the block index. Block are grouped together into group which are the various pkt3 group of config, context, resource, Pipe state build a list of register each state want to modify, beside register value it also give a register mask so only subpart of a register can be updated by a given pipe state (the oring is in the winsys) There is no prebuild register list or define for each pipe state. Once pipe state are built they are bound to the winsys context. Each of this functions will go through the list of register and will find into which block each reg falls and will update the value of the block with proper masking (vs/ps resource/constant are specialized variant with somewhat limited capabilities). Each block modified by r600_context_pipe_state_set* is marked as dirty and we update a count of dwords needed to emit all dirty state so far. r600_context_pipe_state_set* should be call only when pipe context change some of the state (thus when pipe bind state or set state) Then to draw primitive you make a call to r600_context_draw void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw) It will check if there is enough dwords in current cs buffer and if not will flush. Once there is enough room it will copy packet from dirty block and then add the draw packet3 to initiate the draw. The flush will send the current cs, reset the count of dwords to 0 and remark all states that are enabled as dirty and recompute the number of dwords needed to send the current context. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-09-17r600g: Fixed the shift in S_02880C_KILL_ENABLE.Tilman Sauerbeck
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
2010-09-17r600g: Enable PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED.Tilman Sauerbeck
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
2010-09-17r600g: Only set PA_SC_EDGERULE on rv770 and greater.Tilman Sauerbeck
This is what xf86-video-ati and r600c do. Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
2010-09-17r600g: Added DB_SHADER_CONTROL defines.Tilman Sauerbeck
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
2010-09-17r600g: Formatting fixes.Tilman Sauerbeck
Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
2010-09-18r600g: oops got the use_mem_constant the wrong way around.Dave Airlie
this fixes evergreen gears again.