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This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
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Bug #21691.
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The docs actually explain this, but not in a terribly clear manner.
This nearly fixes the piglit cubemap testcase, except that something's
going wrong with the nearest filtering at 2x2 sizes in the testcase.
Looks good by visual inspection, though.
Bug #21692
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Makefile.template
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The most egregious, and the one the bug report and failure in the cubemap
demo were about was introduced with intel_mipmap_pitch_align(), where a
"* 2" for the pitch calculation was lost. The base size < 32 case also
failed to align, which may have caused problems with render to texture.
Another bug would have broken 2x2/1x1 base mipmap levels by placing the
data where the hardware wouldn't look for it.
Other bugs remain with the layout of the small mipmap faces (hardware looks
for them in X,Y,Z,-X,-Y,-Z order along the bottom row, but we lay them out
X,-X,Y,-Y,Z,-Z).
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Also clean up some other miscellaneous formatting nits while I'm at it.
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mipmap pitches must account for the device alignment requirements, which
used to be fairly simple; just align to a 4-byte boundary. However, to allow
textures to be drawn to under TTM, they now need to be aligned to a 64-byte
boundary. Placing all of the alignment constraints in a single function
allows this new constraint to be applied uniformly.
There was some pitch constraining code in intel_miptree_create, but that was
modifying the pitch long after the miptree had been layed out, so it only
served to wreck the mipmap and cause rendering errors.
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