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path: root/src/mesa/drivers/dri/i915
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2008-02-25intel: Add missing include file to silence last couple of warnings.Kristian Høgsberg
2008-02-25intel: Initialize color and spec arrays in LOCAL_VARS macro.Kristian Høgsberg
Avoids spamming compilation output with tons of warnings about use of possibly uninitialized variables.
2008-02-22intel: Merge intel_context.c from i915 and i965.Kristian Høgsberg
2008-02-22Merge {i915,i965}/intel_context.h as intel/intel_context.hKristian Høgsberg
2008-02-22Use drm_i915_sarea instead of drmI830Sarea and remove i830_common.hAlan Hourihane
2008-02-15Add E7221 variant to i915.Adam Jackson
2008-02-15i915: set fogcoord to (f,0,0,1). fix #10788 issue on 915.Xiang, Haihao
2008-02-14Hook up i915 driver to new DRI2 infrastructure.Kristian Høgsberg
2008-02-13[intel] Fix 965 rendering with non-TTM by merging intel_ioctl between 915/965.Eric Anholt
The 965 path wasn't setting pClipRects for batch submission since it didn't want kernel cliprect handling before. The 915 path also grew the INTEL_NO_HW=1 option for testing just driver overhead.
2008-02-06[915] Fix COS function using same plan as SIN.Eric Anholt
The previous COS function failed badly outside of [-pi/2, pi/2].
2008-02-06[915] Use a quartic term to improve the accuracy of SIN results.Eric Anholt
This is described in the link in the comment, and is the same technique that r300 uses.
2008-02-06[915] Fix fp SIN function, and use a quadratic approximation instead of Taylor.Eric Anholt
The Taylor series notably fails at producing sin(pi) == 0, which leads to discontinuity every 2*pi. The quadratic gets us sin(pi) == 0 behavior, at the expense of going from 2.4% THD with working Taylor series to 3.8% THD (easily seen on comparative graphs of the two). However, our previous implementation was producing sin(pi) < -1 and worse, so any reasonable approximation is an improvement. This also fixes the repeating behavior, where the previous implementation would repeat sin(x) for x>pi as sin(x % pi) and the opposite for x < -pi.
2008-01-22[intel] Clean up references to screen buffer metrics.Kristian Høgsberg
The screen wide info such as pitch and cpp are obsoleted by the FBO changes, so clean up the last few references to those, except for setting up the legacy screen regions.
2008-01-17[intel] Make the no_rast option be standard driconf instead of INTEL_NO_RAST.Eric Anholt
2008-01-17[i915] Fix driver from cliprects changes, and clean up state emission.Eric Anholt
The fix for pageflipping with cliprects ended up causing a batch flush at an inopportune time, which is fixed by moving it up. Additionally, the recovery code for handling batch wraps at bad times is replaced by just checking for the space up front, and using a no_batch_wrap assert like on 965 to make sure that we weren't wrong about how much space that was.
2008-01-14[i915] Fix recursive lock hang in intelContendedLock handling.Eric Anholt
2008-01-10[intel] Add more cliprect modes to cover other meanings for batch emits.Eric Anholt
The previous change gave us only two modes, one which looped over the batch per cliprect (3d drawing) and one that didn't (state updeast). However, we really want 4: - Batch doesn't care about cliprects (state updates) - Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing) - Batch needs to be executed just once (region fills, copies, etc.) - Batch already includes cliprect handling, and must be flushed by unlock time (copybuffers, clears). All callers should now be fixed to use one of these states for any batchbuffer emits. Thanks to Keith Whitwell for pointing out the failure.
2008-01-09[intel] Simplify intelCreateBuffer() a bit.Kristian Høgsberg
Drop a bunch of unused arguments from intel_create_renderbuffer() and introduce intel_renderbuffer_set_region() to set the region for a renderbuffer.
2008-01-09[intel] Rename lost_hardware vtbl entry to new_batch.Eric Anholt
Both drivers have ended up relying on lost_hardware being called after each batch buffer, so update the name. This removes one of the calls on 965 whic h was outside of the batchbuffer handling code and just duplicating what had already happened through batchbuffer handling.
2008-01-09[intel] Clean up cliprect handling in intel drivers.Eric Anholt
In particular, batch buffers are no longer flushed when switching from CLIPRECTS to NO_CLIPRECTS or vice versa, and 965 just uses DRM cliprect handling for primitives instead of trying to sneak in its own to avoid the DRM stuff. The disadvantage is that we will re-execute state updates per cliprect, but the advantage is that we will be able to accumulate larger batch buffers, which were proving to be a major overhead.
2008-01-09[intel] Remove the dead intel->need_flush member.Eric Anholt
2008-01-07i915: Keith Whitwell's swizzling TEX patch. fix #8283Xiang, Haihao
2008-01-06Replace gl_framebuffer's _ColorDrawBufferMask with _ColorDrawBufferIndexesBrian
Each array element is now a BUFFER_x token rather than a BUFFER_BIT_x bitmask. The number of active color buffers is specified by _NumColorDrawBuffers. This builds on the previous DrawBuffer changes and will help with drivers implementing GL_ARB_draw_buffers.
2008-01-06Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.Brian
These fields are no longer indexed by shader output. Now, we just have a simple array of renderbuffer pointers. If the shader writes to gl_FragData[i], send those colors to the N _ColorDrawBuffers. Otherwise, replicate the single gl_FragColor (or the fixed-function color) to the N _ColorDrawBuffers. A few more changes and simplifications can follow from this...
2008-01-04i915: don't validate PS program when falling back to softwareXiang, Haihao
rendering. fix #12786
2008-01-03 fix fd.o bug #13761Zou Nan hai
MRD computation is now changed in mesa core
2008-01-02i915: Needn't adjust pixel centers. fix #12944Xiang, Haihao
2007-12-25i915: apply commit a0a5e8cfc04c14873441b50f7d594ef11806b9a8 from 965.Xiang, Haihao
fix #11925
2007-12-22fix GL_LINE_LOOP with drivers using own render pipeline stage (#12410, #13527)Roland Scheidegger
primitive needs to include the begin/end flags (broken since vbo-0.2). Should fix missing first/last line segment on gamma, i810, i915, mga, r200, radeon, s3v, savage, unichrome (r300 already correct). Tested on r200, fixes #13527.
2007-12-21[intel] Move some pixel path support from drivers to shared.Eric Anholt
2007-12-21intel: cast a pointer to unsigned long, avoid potential error.Xiang, Haihao
2007-12-20[intel] Fix and reenable (software) SGIS_generate_mipmapEric Anholt
The core problem was that _mesa_generate_mipmap was not respecting RowStride of the source image. Additionally, the intel private data associated with the images (level and face) was not being initialized for the _mesa_generate_mipmap-generated images.
2007-12-20[i915] Move meta_draw_quad into the vtbl with other meta operations.Eric Anholt
2007-12-20i915: avoid dead lock in intel_meta_draw_poly. fix #13696Xiang, Haihao
2007-12-18[915] Free dri_bufmgr after mesa context data.Eric Anholt
Fixes a crash when buffer objects are left around until context destroy.
2007-12-18[915] Make polygon stipple use pre-unpacked pixel data.Eric Anholt
This fixes a crash when stippling using data from a PBO.
2007-12-18[Intel] Centralize mipmap pitch computations.Keith Packard
mipmap pitches must account for the device alignment requirements, which used to be fairly simple; just align to a 4-byte boundary. However, to allow textures to be drawn to under TTM, they now need to be aligned to a 64-byte boundary. Placing all of the alignment constraints in a single function allows this new constraint to be applied uniformly. There was some pitch constraining code in intel_miptree_create, but that was modifying the pitch long after the miptree had been layed out, so it only served to wreck the mipmap and cause rendering errors.
2007-12-13[intel] Enable INTEL_DEBUG=bufmgr output in TTM mode as well as classic.Eric Anholt
2007-12-12[intel] Move bufmgr back to context instead of screen, fixing glthreads.Eric Anholt
Putting the bufmgr in the screen is not thread-safe since the emit_reloc changes. It also led to a significant performance hit from pthread usage for the attempted thread-safety (up to 12% of a cpu spent on refcounting protection in single-threaded 965). The motivation had been to allow multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
2007-12-07[965] Convert the driver to dri_bufmgr interface and enable TTM.Eric Anholt
This is currently believed to work but be a significant performance loss. Performance recovery should be soon to follow. The dri_bo_fake_disable_backing_store() call was added to allow backing store disable like bufmgr_fake.c did, which is a significant performance win (though it's missing the no-fence-subdata part). This commit is a squash merge of the 965-ttm branch, which had some history I wanted to avoid pulling due to noisiness and brokenness at many points for git-bisecting.
2007-12-07i915: fix the error in the previos commit.Xiang, Haihao
2007-12-07i915: Check the program size when uploading a program. fix bug 13494Xiang, Haihao
2007-12-03i915: Fix up state changes for i8xx.Michel Dänzer
2007-11-29[i915] Make INTEL_DEBUG=bufmgr actually do things for bufmgr_fake.Eric Anholt
2007-11-26i915: Catch cases where not all state is emitted for a new batchbuffer.Keith Whitwell
This could lead to incorrect rendering or even lockups.
2007-11-25intel: Fix relative symlinks.Michel Dänzer
2007-11-16[intel] Add 965 support to shared intel_blit.cEric Anholt
This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine.
2007-11-16[intel] Move additional code to be shared from intel_context.h to intel/.Eric Anholt
2007-11-16[intel] Move intel_tex.h into place, forgotten in the previous commit.Eric Anholt
2007-11-16[i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them.Eric Anholt