summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri/i965/Makefile
AgeCommit message (Collapse)Author
2011-01-19i965/fs: Add an instruction scheduler.Eric Anholt
Improves performance of my GLSL demo by 5.1% (+/- 1.4%, n=7). It also reschedules the giant multiply tree at the end of glsl-fs-convolution-1 so that we end up not spilling registers, producing the expected level of performance.
2010-12-06i965: Nuke brw_wm_glsl.c.Eric Anholt
It was only used for gen6 fragment programs (not GLSL shaders) at this point, and it was clearly unsuited to the task -- missing opcodes, corrupted texturing, and assertion failures hit various applications of all sorts. It was easier to patch up the non-glsl for remaining gen6 changes than to make brw_wm_glsl.c complete. Bug #30530
2010-10-21i965: Split register allocation out of the ever-growing brw_fs.cpp.Eric Anholt
2010-10-07i965: Normalize cubemap coordinates like is done in the Mesa IR path.Eric Anholt
Fixes glsl-fs-texturecube-2-*
2010-08-26i965: Add new pass to split vectors into scalar variablesEric Anholt
Combined with the previous pass, this lets other optimization passes do their work thanks to ir_tree_grafting. Still have regression in instruction count with INTEL_NEW_FS, but register count is even better.
2010-08-26i965: Add a pass for the FS to reduce vector expressions down to scalar.Eric Anholt
This is a step towards implementing a GLSL IR backend for the 965 fragment shader. Because it has downsides with the current codegen, it is hidden under the environment variable INTEL_NEW_FS. This results in an increase in instruction count at the moment (1444 -> 1752 for glsl-fs-raytrace, 345 -> 359 on my demo), because dot products are turned into a series of multiplies and adds instead of a custom expansion of MULs and MACs, and by not splitting the variable types up we don't get tree grafting and thus there are extra moves of temporary storage. However, register count drops for the non-GLSL path (64 -> 56 on my demo shader) because the register allocator sees all the sub-operations.
2010-08-26i965: Start building 965 FS backend.Eric Anholt
2010-07-27intel: Remove unused intel/server filesKristian Høgsberg
2010-06-11i965: Set the CC VP state immediately on state change.Eric Anholt
The cache lookup of these two little floats was .12% of total CPU time on firefox-talos-gfx because we did it any time commonly-changed state changed. On the other hand, updating the CC VP bo immediately whenver CC VP state changes is a .07% overhead due to putting a driver hoook in glEnable().
2010-04-28intel: Only register ES2 extensions for ES2 contextsKristian Høgsberg
2010-03-12i965: Fix up VS DP4 sequences to avoid dependency control.Eric Anholt
This is recommended by the B-Spec. I wasn't able to measure any difference in ETQW.
2010-03-06dri: drop MINIGLX_SOURCESGeorge Sapountzis
2010-02-25i965: Set up the SNB sampler state pointers.Eric Anholt
2010-02-25i965: Untested Sandybridge WM packets.Eric Anholt
2010-02-25i965: Untested Sandybridge SF setup.Eric Anholt
2010-02-25i965: Add Sandybridge viewport setup.Eric Anholt
2010-02-25i965: Add Sandybridge scissor state.Eric Anholt
2010-02-25i965: Set up the SNB URB.Eric Anholt
even with vs disabled, still doesn't work.
2010-02-25i965: Add untested REJECT_ALL clip state.Eric Anholt
2010-02-25i965: Add untested passthrough GS setup.Eric Anholt
2010-02-25i965: Add untested Sandybridge passthrough VS setup.Eric Anholt
2010-02-25i965: Start adding support for the Sandybridge CC unit.Eric Anholt
2010-01-04intel: Remove client-side vblank codeKristian Høgsberg
2010-01-04Check for libdrm_$chipset.pc when neededKristian Høgsberg
This adds missing pkg-config lookup for intel and moves the radeon lookup into a case...esac so it's only looked up when one or more of the radeon drivers are enabled.
2009-10-16mesa: lift default symlinks target into Makefile.templateBrian Paul
Driver Makefiles can still add symlink dependencies/rules if needed.
2009-09-28intel: Drop my generatemipmap code in favor of the new shared code.Eric Anholt
2009-09-03intel: Add support for ARB_sync.Eric Anholt
We currently weasel out of supporting the timeout parameter, but otherwise this extension looks ready, and should make the common case happy.
2009-08-04i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out, and running intel-gen4disasm on it.
2009-06-19intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt
2009-05-08intel: Add a metaops version of glGenerateMipmapEXT/SGIS_generate_mipmaps.Eric Anholt
In addition to being HW accelerated, it avoids the incorrect (black) rendering of the mipmaps that SW was doing in fbo-generatemipmap. Improves the performance of the mipmap generation and drawing in fbo-generatemipmap by 30%.
2009-05-06i965: Disentangle VS constant surface state from WM surface state.Eric Anholt
Also, only create VS surface state if there's a VS constant buffer to be uploaded, and set the contents of the buffer at the same time as creation.
2009-02-02i965: Delete old metaops code now that there are no remaining consumers.Eric Anholt
2009-01-26intel: move intelInitExtensions() and related code into new intel_extensions.cBrian Paul
2009-01-26intel: move glClear-related code into new intel_clear.c fileBrian Paul
2009-01-26intel: Move swap-related functions from intel_buffers.c to new ↵Brian Paul
intel_swapbuffers.c
2009-01-22intel: remove/disable the "paired depth/stencil" codeBrian Paul
We only allow combined depth+stencil renderbuffers so the complicated code for splitting and combining separate depth and stencil buffers is no longer needed.
2009-01-07i965: Remove dead brw_vs_tnl.cEric Anholt
2008-10-09i965: Actually hook up the accelerated DrawPixels support.Eric Anholt
2008-10-07i965: Add ARB_occlusion_query support.Eric Anholt
2008-09-10intel: track move of bo_exec from drivers to bufmgr.Eric Anholt
2008-09-10intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.Eric Anholt
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-06-24Merge commit 'origin/master' into drm-gemEric Anholt
2008-06-24intel: Merge check_blit_fragment_ops between i915/i965.Eric Anholt
Both had some useful bits for the other.
2008-06-03[intel] Convert drivers to using libdrm bufmgr code.Eric Anholt
2008-05-07GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.Eric Anholt
The GEM flags are much more descriptive for what we need. Since this makes bufmgr_fake rather device-specific, move it to the intel common directory. We've wanted to do device-specific stuff to it before.
2008-05-02Add intel_bufmgr_gem for new graphics execution manager.Eric Anholt
2008-02-14i965: remove unused hal hooksDave Airlie
These don't appear to have ever been used.
2007-12-20[965] Enable EXT_framebuffer_object.Eric Anholt
To do so, merge the remainnig necessary code from the buffers, blit, span, and screen code to shared, and replace it with those.
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-16 06:07:44 +0000