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path: root/src/mesa/drivers/dri/i965/brw_cc.c
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2010-06-12i965: Stream out CC unit state.Eric Anholt
before: [ # ] backend test min(s) median(s) stddev. count [ 0] gl firefox-talos-gfx 31.791 32.287 1.11% 6/6 after: [ 0] gl firefox-talos-gfx 31.198 31.675 0.96% 6/6
2010-06-11i965: GC the last two arguments to brw_cache_data.Eric Anholt
Now that the binding table is streamed indirect state, they were always NULL/0.
2010-06-11i965: Set the CC VP state immediately on state change.Eric Anholt
The cache lookup of these two little floats was .12% of total CPU time on firefox-talos-gfx because we did it any time commonly-changed state changed. On the other hand, updating the CC VP bo immediately whenver CC VP state changes is a .07% overhead due to putting a driver hoook in glEnable().
2010-06-08intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.Eric Anholt
The new API makes so much more sense, I'd like to forget how the old one worked.
2010-06-08intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.Eric Anholt
The slightly less mechanical change of converting the emit_reloc calls will follow.
2010-01-25Merge branch 'mesa_7_7_branch'Brian Paul
Conflicts: src/mesa/drivers/dri/intel/intel_screen.c src/mesa/drivers/dri/intel/intel_swapbuffers.c src/mesa/drivers/dri/r300/r300_emit.c src/mesa/drivers/dri/r300/r300_ioctl.c src/mesa/drivers/dri/r300/r300_tex.c src/mesa/drivers/dri/r300/r300_texstate.c
2010-01-22i965: Remove unnecessary headers.Vinson Lee
2010-01-19i965: Allow for variable-sized auxdata in the state cache.Eric Anholt
Everything has been constant-sized until now, but constant buffer handling changes will make us want some additional variable sized array.
2009-12-14i965: Use current draw buffer instead of drawable visual to get alpha bitsIan Romanick
Use the currently bound draw buffer instead of the visual from the drawable used to create the context. This cause problems generating mipmaps for an RGBA texture in an RGB context. This fixes the failure in piglit's glsl-lod-bias test reported in bug #25614.
2009-12-10i965: Fix handling of drawing to MESA_FORMAT_XRGB8888Ian Romanick
It turns out that 965 and friends cannot actually render to an xRGB surfaces. Instead, the surface has to be RGBA with writes to alpha disabled and the blend function modified to always use 1.0 for destination alpha.
2009-11-06i965: Always pass the size argument to brw_cache_data.Eric Anholt
This keeps the individual state files from having to export their structures for brw_state_cache initialization.
2009-10-29i965: Fix fallout from ARB_depth_clamp enablement that broke glDepthRange.Eric Anholt
If a backwards glDepthRange was supplied (as with the old Quake no-z-clearing hack), the hardware would have always clamped because we weren't clamping to the min of near/far and the max of near/far. Also, we shouldn't be clamping to near/far at all when not in depth clamp mode (this usually didn't matter since near/far are usually the same as the 0.0, 1.0 clamping you do for fixed-point depth). This should fix funny depth issues in PlaneShift, and fixes piglit depth-clamp-range
2009-09-08i965: Add support for ARB_depth_clamp.Eric Anholt
2009-03-02mesa: use Stencil._Enabled field instead of Stencil.EnabledBrian Paul
2009-02-02i965: Remove brw->attribs now that we can just always look in the GLcontext.Eric Anholt
2009-01-23Track two sets of back-face stencil stateIan Romanick
Track separate back-face stencil state for OpenGL 2.0 / GL_ATI_separate_stencil and GL_EXT_stencil_two_side. This allows all three to be enabled in a driver. One set of state is set via the 2.0 or ATI functions and is used when STENCIL_TEST_TWO_SIDE_EXT is disabled. The other is set by StencilFunc and StencilOp when the active stencil face is set to BACK. The GL_EXT_stencil_two_side spec has more details. http://opengl.org/registry/specs/EXT/stencil_two_side.txt
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul
Makefile.template
2008-09-10intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.Eric Anholt
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-08intel-gem: Update to new check_aperture API for classic mode.Eric Anholt
To do this, I had to clean up some of 965 state upload stuff. We may end up over-emitting state in the aperture overflow case, but that should be rare, and I'd rather have the simplification of state management.
2008-08-08965: cleanups to state emission from aperture checking and state ordering.Eric Anholt
2008-06-11[intel-gem] Chase domain flag renaming in the DRM.Eric Anholt
This is an API breakage only.
2008-06-03[intel] Convert drivers to using libdrm bufmgr code.Eric Anholt
2008-05-07GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.Eric Anholt
The GEM flags are much more descriptive for what we need. Since this makes bufmgr_fake rather device-specific, move it to the intel common directory. We've wanted to do device-specific stuff to it before.
2008-04-18i965: initial attempt at fixing the aperture overflowDave Airlie
Makes state emission into a 2 phase, prepare sets things up and accounts the size of all referenced buffer objects. The emit stage then actually does the batchbuffer touching for emitting the objects. There is an assert in dri_emit_reloc if a reloc occurs for a buffer that hasn't been accounted yet.
2008-01-16[965] Rename depth_mask in CC key to depth_write, since it's a boolean enable.Eric Anholt
2008-01-16[965] Fix the type of alpha_ref in CC key, fixing ppracer rendering.Eric Anholt
2008-01-03[intel] Convert relocations to not be cleared out on buffer submit.Eric Anholt
We have two consumers of relocations. One is static state buffers, which want the same relocation every time. The other is the batchbuffer, which gets thrown out immediately after submit. This lets us reduce repeated computation for static state buffers, and clean up the code by moving relocations nearer to where the state buffer is computed.
2008-01-02[965] Convert CC unit to use a cache key instead of brw_cache_data.Eric Anholt
2007-12-21[965] Fix and enable separate stencil.Eric Anholt
Note that this does not enable GL_EXT_stencil_two_side, because Mesa's computed _TestTwoSide ends up respecting only STENCIL_TEST_TWO_SIDE_EXT (defaults to GL_FALSE), even if the application uses only GL 2.0 / ATI entrypoints.
2007-12-14[965] Replace the state cache suballocator with direct dri_bufmgr use.Eric Anholt
The user-space suballocator that was used avoided relocation computations by using the general and surface state base registers and allocating those types of buffers out of pools built on top of single buffer objects. It also avoided calls into the buffer manager for these small state allocations, since only one buffer object was being used. However, the buffer allocation cost appears to be low, and with relocation caching, computing relocations for buffers is essentially free. Additionally, implementing the suballocator required a don't-fence-subdata flag to disable waiting on buffer maps so that writing new data didn't block on rendering using old data, and careful handling when mapping to update old data (which we need to do for unavoidable relocations with FBOs). More importantly, when the suballocator filled, it had no replacement algorithm and just threw out all of the contents and forced them to be recomputed, which is a significant cost. This is the first step, which just changes the buffer type, but doesn't yet improve the hash table to not result in full recompute on overflow. Because the buffers are all allocated out of the general buffer allocator, we can no longer use the general/surface state bases to avoid relocations, and they are set to 0 instead.
2007-05-03add some #includes to silence warningsBrian
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.