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In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
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1. increase clip thread number to 2
2. do cliptest for -rhw
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between the vertex cache, the vertex shader and the clipping stages,
all of which are competitors for URB entries assigned to the VS unit.
This change reduces the maximum number of clip and VS threads by
enough to ensure that they cannot consume all the available URB
entries, and then reduces the number somewhat more up to an arbitary
amount I discovered by trial and error. Unfortunately trial and error
solutions don't inspire total confidence...
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This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
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