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path: root/src/mesa/drivers/dri/i965/brw_defines.h
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2011-02-25i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.Kenneth Graunke
From volume 4, page 161 of the public i965 documentation.
2011-02-08i965: Rename a few more commands to match the documentation.Kenneth Graunke
2011-01-10i965: Add #defines for HiZ and separate stencil buffer commands.Kenneth Graunke
2011-01-10i965: Rename more #defines to 3DSTATE rather than CMD or CMD_3D.Kenneth Graunke
Again, this makes it match the documentation.
2011-01-10i965: Remove unused #defines which only contain the sub-opcode.Kenneth Graunke
Most _3DSTATE defines contain the command type, sub-type, opcode, and sub-opcode (i.e. 0x7905). These, however, contain only the sub-opcode (i.e. 0x05). Since they are inconsistent with the rest of the code and nothing uses them, simply delete them. The _3DOP and _3DCONTROL defines seemed similar, and were also unused.
2011-01-06i965: Rename various gen6 #defines to match the documentation.Kenneth Graunke
This should make it easier to cross-reference the code and hardware documentation, as well as clear up any confusion on whether constants like CMD_3D_WM_STATE mean WM_STATE (pre-gen6) or 3DSTATE_WM (gen6+). This does not rename any pre-gen6 defines.
2011-01-04i965: Add support for SRGB DXT1 formats.Eric Anholt
This makes fbo-generatemipmap-formats GL_EXT_texture_sRGB-s3tc match fbo-generatemipmap-formats GL_EXT_texture_compression_s3tc and swrast in bad DXT1_RGBA alpha=0 handling, but it means we won't unpack and repack someone's textures into uncompressed SARGB8 format.
2010-12-16i965: Set the alternative floating point mode on gen6 VS and WM.Eric Anholt
This matches how we did the math instructions pre-gen6, though it applies to non-math as well. Fixes vp1-LIT test 2 (degenerate case: 0 ^ 0 -> 1)
2010-12-10i965: support for two-sided lighting on SandybridgeXiang, Haihao
VS places color attributes together so that SF unit can fetch the right attribute according to object orientation. This fixes light issue in mesa demo geartrain, projtex.
2010-12-06i965: Add support for the instruction compression bits on gen6.Eric Anholt
Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-10-28i965: Add user clip planes support to gen6.Eric Anholt
Fixes piglit user-clip, and compiz desktop switching when dragging a window and using just 2 desktops. Bug #30446.
2010-10-26i965: Use SENDC on the first render target write on gen6.Eric Anholt
This is apparently required, as the thread will be initiated while it still has dependencies, and this is what waits for those to be resolved before writing color.
2010-10-06i965: Add some clarification of the WECtrl field.Eric Anholt
2010-09-28i965: force zero in clipper to ignore RTAIndex on sandybridgeZhenyu Wang
2010-08-30i965: Add support for texturing with bias to i965 FS backend.Eric Anholt
Fixes 5 piglit tests for bias. Note that LOD is a 1.30 feature and not yet supported.
2010-07-26i965: Clean up a few magic numbers to use brw_defines.h defs.Eric Anholt
2010-07-21i965: Fix the DP read msg_control definitions other than plain OWORD.Eric Anholt
2010-07-08i965: Add definitions for Sandybridge DP write/read messages.Zhenyu Wang
2010-06-14i965: correct the gen6 line stipple enable define.Zhenyu Wang
2010-05-18 gen6 fix: fix a wrong bit in binding_table_pointerZou Nan hai
2010-04-21intel: Clean up chipset name and gen num for IronlakeZhenyu Wang
Rename old IGDNG to Ironlake, and set 'gen' number for Ironlake as 5, so tracking the features with generation num instead of special is_ironlake flag. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-03-22i965: Correct copy and wasted field shifts for SNB GS URB.Eric Anholt
2010-03-10i965: Use the PLN instruction when possible in interpolation.Eric Anholt
Saves an instruction in PINTERP, LINTERP, and PIXEL_W from brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have to be laid out differently.
2010-02-25i965: Fix the SNB VE valid bit.Eric Anholt
So, when the docs say that 0 means enabled now? That's a lie.
2010-02-25i965: Fix the SNB clip near VP API bit.Eric Anholt
2010-02-25i965: Add SNB math opcode support.Eric Anholt
This is untested at this point.
2010-02-25i965: Set up the SNB sampler state pointers.Eric Anholt
2010-02-25i965: Add a couple SNB state packets I saw in other batchbuffer dumps.Eric Anholt
2010-02-25i965: Re-disable the VS.Eric Anholt
There's stuff that needs to happen in the ISA before we can play with actually executing anything in the VS.
2010-02-25i965: Untested Sandybridge WM packets.Eric Anholt
2010-02-25i965: Untested Sandybridge SF setup.Eric Anholt
2010-02-25i965: Fix up Sandybridge GS reg definitionsEric Anholt
2010-02-25i965: fix typo in SNB VS defines commentEric Anholt
2010-02-25i965: fix typo in SNB GS register definesEric Anholt
2010-02-25i965: Add Sandybridge viewport setup.Eric Anholt
2010-02-25i965: Add Sandybridge scissor state.Eric Anholt
2010-02-25i965: Fix some defines of gen6 regs from docs comparison.Eric Anholt
2010-02-25i965: Reconnect the index/vertex setup.Eric Anholt
2010-02-25i965: Set up the SNB URB.Eric Anholt
even with vs disabled, still doesn't work.
2010-02-25i965: Add untested REJECT_ALL clip state.Eric Anholt
2010-02-25i965: Add untested passthrough GS setup.Eric Anholt
2010-02-25i965: Add untested Sandybridge passthrough VS setup.Eric Anholt
2010-02-25i965: Start adding support for the Sandybridge CC unit.Eric Anholt
2010-02-25i965: Set up sandybridge binding table pointers but don't enable it yet.Eric Anholt
It hangs the GPU at the clipper stage, presumably because we're lacking other setup.
2009-12-22intel: Replace IS_965 checks with context structure usage.Eric Anholt
Saves another 600 bytes or so of code.
2009-12-22intel: Replace IS_G4X() across the driver with context structure usage.Eric Anholt
Saves ~2KB of code.
2009-11-13i965: Clean up Ironlake sampler type definitions.Eric Anholt
They're the same regardless of execution width for 8, 4x2, and 16.
2009-08-04i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out, and running intel-gen4disasm on it.
2009-07-13i965: add support for new chipsetsXiang, Haihao
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-03-28i965: srgb texture fixesRoland Scheidegger
i965 can either do SRGBA8_REV format or SARGB8 format, but not SRGBA8. Could add SRGBA8_REV support to mesa, but simply use SARGB8 for now. While here, also add true srgb luminance / luminance_alpha support - unfortunately the published docs fail to mention which asics support this, tested on g43 so assume this works on any g4x.