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path: root/src/mesa/drivers/dri/i965/brw_defines.h
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2008-11-02i965: Merge GM45 into the G4X chipset define.Eric Anholt
The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-07-25Merge branch 'master' into drm-gemIan Romanick
Conflicts: src/mesa/drivers/dri/common/dri_bufmgr.c src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-07-08i965: official name for GM45 chipsetXiang, Haihao
2008-06-26intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing.Eric Anholt
Most of these were to ensure that caches got synchronized between 2d (or meta) rendering and later use of the target as a source, such as for texture miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(), which just drops an MI_FLUSH. Most of the remainder were to ensure that REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped. Those are now replaced by automatically flushing those when dropping the lock.
2008-05-23Emit a flush after the swapbuffers blit, so contents end up on the screen.Eric Anholt
Otherwise, since the MI_FLUSH at the end of every batch had been removed, non-automatic-flushing chips (965) wouldn't get flushed and apps with static rendering would get partial screen contents until the server's blockhandler flush kicked in.
2008-02-04[965] Replace VEP/VBP state structures with inline batch emits.Eric Anholt
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2007-08-02 fix fd.o bug #11804Zou Nan hai
glPolygonMode with point sprite on i965
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.