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path: root/src/mesa/drivers/dri/i965/brw_disasm.c
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2010-10-26i965: Add disasm for the flag register.Eric Anholt
2010-10-26i965: Use SENDC on the first render target write on gen6.Eric Anholt
This is apparently required, as the thread will be initiated while it still has dependencies, and this is what waits for those to be resolved before writing color.
2010-10-06i965: Add some clarification of the WECtrl field.Eric Anholt
2010-10-06i965: Fix up IF/ELSE/ENDIF for gen6.Eric Anholt
The jump delta is now in the part of the instruction where the destination fields used to be, and the src args are ignored (or not, for the new non-predicated IF that we don't use yet).
2010-10-04i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.Eric Anholt
It instead sensibly appears in the src0 slot.
2010-09-28i965: disasm quarter and write enable instruction control on sandybridgeZhenyu Wang
2010-08-28i965: Add disasm for gen5 sampler messages.Eric Anholt
2010-08-20i965: Add AccWrCtl support on Sandybridge.Zhenyu Wang
Whenever the accumulator results are needed, this bit must be set.
2010-08-20i965: Mention the mlen and rlen for URB reads.Zhenyu Wang
2010-08-20i965: Adjust disasm of subreg numbers to be in units of the register type.Zhenyu Wang
This makes reading the code easier when matching up to the specs, which also use this format.
2010-08-16i965: Add disasm for Compr4 instruction compression.Eric Anholt
2010-07-22i965: Fix the disasm output for da16 src widths.Eric Anholt
This has confused me twice now. It's a fixed width of 4 (usually a region description of <4,4,1>), not 1. If it was 1, we'd have been skipping all over register space.
2010-07-21i965: Add disasm for dataport reads (register unspilling).Eric Anholt
2010-07-08i965: Add disasm for SEND mlen/rlen on Sandybridge.Eric Anholt
2010-07-08i965: Fix disasm of a SEND's mlen and rlen on Ironlake.Eric Anholt
2010-07-08i965: Add decode for Sandybridge DP write messages.Zhenyu Wang
2010-05-14i965: Parse the ff_sync URB send opcode on Ironlake disasm.Eric Anholt
2010-05-14i965: Dump out the correct shared function for SEND on Ironlake.Eric Anholt
2010-03-22i965: Add disasm for SNB MATH opcode.Eric Anholt
2010-03-10i965: Use the PLN instruction when possible in interpolation.Eric Anholt
Saves an instruction in PINTERP, LINTERP, and PIXEL_W from brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have to be laid out differently.
2010-03-10i965: Print the offset for IFF in disasmEric Anholt
2010-03-09i965: Print the offsets for WHILE and BREAK in disasm.Eric Anholt
2009-12-31Merge branch 'mesa_7_7_branch'Brian Paul
Conflicts: configs/darwin src/gallium/auxiliary/util/u_clear.h src/gallium/state_trackers/xorg/xorg_exa_tgsi.c src/mesa/drivers/dri/i965/brw_draw_upload.c
2009-12-26i965: Fix setup of immediate types for gen4 disasm.Eric Anholt
Caught by clang.
2009-12-24i965: Add missing va_end.Vinson Lee
2009-08-04i965: Print out ELSE and ENDIF src1 arguments like IF does.Eric Anholt
2009-08-04i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out, and running intel-gen4disasm on it.
2009-08-04i965: Initial import of disasm code from intel-gen4asm.Eric Anholt
There's a bunch of stuff from gen4asm and gpu-tools that we probably want to make into a library instead of cargo-culting it around.