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path: root/src/mesa/drivers/dri/i965/brw_eu.h
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2009-04-17i915: fix broken indirect constant buffer readsBrian Paul
The READ message's msg_control value can be 0 or 1 to indicate that the Oword should be read into the lower or upper half of the target register. It seems that the other half of the register gets clobbered though. So we read into two dest registers then use a MOV to combine the upper/lower halves.
2009-04-16i965: implement relative addressing for VS constant buffer readsBrian Paul
A scatter-read should be possible, but we're just using two READs for the time being.
2009-04-14i965: fix VS constant buffer readsBrian Paul
This mostly came down to finding the right MRF incantation in the brw_dp_READ_4_vs() function. Note: this feature is still disabled (but getting close to done).
2009-04-14i965: checkpoint commit: VS constant buffersBrian Paul
Hook up a constant buffer, binding table, etc for the VS unit. This will allow using large constant buffers with vertex shaders. The new code is disabled at this time (use_const_buffer=FALSE).
2009-04-03i965: added brw_same_reg()Brian Paul
2009-04-03i965: added new brw_dp_READ_4() functionBrian Paul
Used to read float[4] vectors from the constant buffer/surface.
2009-03-13i965: more register number assertionsBrian Paul
2009-03-06i965: bump up BRW_EU_MAX_INSNBrian Paul
This is the size of the intermediate instruction buffer.
2009-02-13i965: rewrite the code for handling shader subroutine callsBrian Paul
Previously, the prog_instruction::Data field was used to map original Mesa instructions to brw instructions in order to resolve subroutine calls. This was a rather tangled mess. Plus it's an obstacle to implementing dynamic allocation/growing of the instruction buffer (it's still a fixed size). Mesa's GLSL compiler emits a label for each subroutine and CAL instruction. Now we use those labels to patch the subroutine calls after code generation has been done. We just keep a list of all CAL instructions that needs patching and a list of all subroutine labels. It's a simple matter to resolve them. This also consolidates some redundant post-emit code between brw_vs_emit.c and brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data fields at the end. Plus, a bunch of new comments.
2009-01-05i965: implement OPCODE_TRUNC (round toward zero) on vertex path.Brian Paul
Also, fix some RNDD vs. RNDZ confusion elsewhere.
2009-01-01i965: comments, clean-ups, re-order some functionsBrian Paul
2008-11-05i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong
OPCODE_NOISE4 coming later.
2008-10-31i965: support destination horiz strides in align1 access mode.Gary Wong
This is required for scatter writes in destination regions to work.
2008-06-21replace __inline and __inline__ with INLINE macroBrian Paul
2008-04-25[i965] short immediate values must be replicated to both halves of the dwordKeith Packard
The 32-bit immediate value in the i965 instruction word must contain two copies of any 16-bit constants. brw_imm_uw and brw_imm_w just needed to copy the value into both halves of the immediate value instruction field.
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2007-12-29fix fd.o bug #13847Zou Nan hai
2007-09-30 fragment shader function call fix, gl_FragCoord fixZou Nan hai
2007-09-29 support continue, fix conditionalZou Nan hai
2007-06-21 support branch and loop in pixel shaderZou Nan hai
most of the sample working with some small modification
2007-04-12 Initial 965 GLSL supportZou Nan hai
2007-02-23Update DRI drivers for new glsl compiler.Brian
Mostly: - update #includes - update STATE_* token code
2007-01-06i965: Avoid branch instructions while in single program flow mode.Eric Anholt
There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.