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The READ message's msg_control value can be 0 or 1 to indicate that the
Oword should be read into the lower or upper half of the target register.
It seems that the other half of the register gets clobbered though. So
we read into two dest registers then use a MOV to combine the upper/lower
halves.
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A scatter-read should be possible, but we're just using two READs for
the time being.
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This mostly came down to finding the right MRF incantation in the
brw_dp_READ_4_vs() function.
Note: this feature is still disabled (but getting close to done).
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Hook up a constant buffer, binding table, etc for the VS unit.
This will allow using large constant buffers with vertex shaders.
The new code is disabled at this time (use_const_buffer=FALSE).
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Used to map drawables, textures and constant buffers to surface binding
table indexes.
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This fixes the random results that were seen when fetching a constant
inside an IF/ELSE clause. Disabling the execution mask ensures that all
the components of the register are written.
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We were accidentally clobbering the next register.
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Used to read float[4] vectors from the constant buffer/surface.
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Haven't seen failures yet, but if/when there are, more investigation will
be done.
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Also, fix some RNDD vs. RNDZ confusion elsewhere.
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The mobile and desktop chipsets are the same, and having them separate is
more typing and more chances to screw up.
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Quoting section 11.3.10, paragraph 10.2 of the 965PRM:
10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is
relaxed from rule 10.1.2. Also note that this rule for destination
horizontal stride is different from that for source as stated in
rule #7.
GM45 gets very angry when rule 10.2 is violated.
Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode)
added support for additional horizontal strides in the ExecSize 1 case, but
failed to notice that mesa occasionally re-purposes a register as a
temporary destination, even though it was constructed as a repeating source
with HorzStride = 0.
While, ideally, we should probably fix the code using these register
specifications, this patch simply rewrites them to use HorzStride 1 as the
pre-58dc8b7 code did.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This is required for scatter writes in destination regions to work.
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A thread switch is implicitly invoked after the issuance of an IF/ELSE/ENDIF
instruction if necessary. Unfortunately it seems sometimes a forced thread
switch is needed.
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to IP pre-increment, and should point to
the first instruction after the do instruction
of the do-while block of code
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most of the sample working with some small modification
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There is an errata for Broadwater that threads don't have the instruction/loop
mask stacks initialized on thread spawn. In single program flow mode, those
stacks are not writable, so we can't initialize them. However, they do get
read during ELSE and ENDIF instructions. So, instead, replace branch
instructions in single program flow mode with predicated jumps (ADD to the ip
register), avoiding use of the more complicated branch instructions that may
fail. This is also a minor optimization as no ENDIF equivalent is necessary.
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
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This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
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