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path: root/src/mesa/drivers/dri/i965/brw_eu_emit.c
AgeCommit message (Expand)Author
2009-04-14i965: checkpoint commit: VS constant buffersBrian Paul
2009-04-09i965: new SURF_INDEX_ macrosBrian Paul
2009-04-08i965: set BRW_MASK_DISABLE flag in "send" instruction in brw_dp_READ_4()Brian Paul
2009-04-03i965: s/GL_FALSE/BRW_COMPRESSION_NONE/Brian Paul
2009-04-03i965: fix response length param in brw_dp_READ_4()Brian Paul
2009-04-03i965: added new brw_dp_READ_4() functionBrian Paul
2009-04-03i965: new and updated commentsBrian Paul
2009-04-03i965: comments for brw_SAMPLE()Brian Paul
2009-03-13i965: add some register number assertionsBrian Paul
2009-02-13i965: minor clean-upsBrian Paul
2009-01-05i965: implement OPCODE_TRUNC (round toward zero) on vertex path.Brian Paul
2008-11-02i965: Merge GM45 into the G4X chipset define.Eric Anholt
2008-11-01Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1Keith Packard
2008-10-31i965: support destination horiz strides in align1 access mode.Gary Wong
2008-08-29i965: force thread switch after IF/ELSE/ENDIF. partial fix for #16882.Xiang, Haihao
2008-08-29i965: mask control for BREAK/CONT/DO/WHILE. partial fix fox #16882Xiang, Haihao
2008-07-08i965: official name for GM45 chipsetXiang, Haihao
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2007-11-27i965: The jump instruction count is addedXiang, Haihao
2007-09-29 support continue, fix conditionalZou Nan hai
2007-06-21 support branch and loop in pixel shaderZou Nan hai
2007-04-12 Initial 965 GLSL supportZou Nan hai
2007-01-06i965: Avoid branch instructions while in single program flow mode.Eric Anholt
2006-09-01fix a couple of cases where a message reg is used as an instruction source.Keith Whitwell
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
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