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path: root/src/mesa/drivers/dri/i965/brw_gs_emit.c
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2010-10-14i965: Fix GS hang on SandybridgeZhenyu Wang
Don't use r0 for FF_SYNC dest reg on Sandybridge, which would smash FFID field in GS payload, that cause later URB write fail. Also not use r0 in any URB write requiring allocate.
2010-06-10mesa: rename src/mesa/shader/ to src/mesa/program/Brian Paul
2010-05-18i965: Remove constant or ignored-by-hw args from FF sync message setup.Eric Anholt
2010-01-25Merge branch 'mesa_7_7_branch'Brian Paul
Conflicts: src/mesa/drivers/dri/intel/intel_screen.c src/mesa/drivers/dri/intel/intel_swapbuffers.c src/mesa/drivers/dri/r300/r300_emit.c src/mesa/drivers/dri/r300/r300_ioctl.c src/mesa/drivers/dri/r300/r300_tex.c src/mesa/drivers/dri/r300/r300_texstate.c
2010-01-22i965: Remove unnecessary headers.Vinson Lee
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt
Saves ~480 bytes of code.
2009-11-11i965: fix EXT_provoking_vertex supportRoland Scheidegger
This didn't work for quad/quadstrips at all, and for all other primitive types it only worked when they were unclipped. Fix up the former in gs stage (could probably do without these changes and instead set QuadsFollowProvokingVertexConvention to false), and the rest in clip stage.
2009-08-04i965: warning fixEric Anholt
2009-07-13i965: add support for new chipsetsXiang, Haihao
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul
Makefile.template
2008-03-18Revert "[i965] make stipple pattern continue across GL_LINE_LOOP and ↵Zou Nan hai
GL_LINE_STRIP" There is no information in GS to determinate when to reset line stipple count, still fallback to software This reverts commit 5a0314b431ab147c6156c3011f4cb54161ba4b25.
2008-03-18[i965] make stipple pattern continue across GL_LINE_LOOP and GL_LINE_STRIPZou Nan hai
2007-01-17I965: fix bug#9625-get the correct PV for quardstripXiang, Haihao
The order of vertices in payload for quardstrip is (0, 1, 3, 2), so the PV for quardstrip is c->reg.vertex[2].
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.
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