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path: root/src/mesa/drivers/dri/i965/brw_gs_emit.c
AgeCommit message (Collapse)Author
2009-08-04i965: warning fixEric Anholt
2009-07-13i965: add support for new chipsetsXiang, Haihao
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul
Makefile.template
2008-03-18Revert "[i965] make stipple pattern continue across GL_LINE_LOOP and ↵Zou Nan hai
GL_LINE_STRIP" There is no information in GS to determinate when to reset line stipple count, still fallback to software This reverts commit 5a0314b431ab147c6156c3011f4cb54161ba4b25.
2008-03-18[i965] make stipple pattern continue across GL_LINE_LOOP and GL_LINE_STRIPZou Nan hai
2007-01-17I965: fix bug#9625-get the correct PV for quardstripXiang, Haihao
The order of vertices in payload for quardstrip is (0, 1, 3, 2), so the PV for quardstrip is c->reg.vertex[2].
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.
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