Age | Commit message (Collapse) | Author |
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1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
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Makefile.template
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GL_LINE_STRIP"
There is no information in GS to determinate when to reset line stipple count, still fallback to software
This reverts commit 5a0314b431ab147c6156c3011f4cb54161ba4b25.
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The order of vertices in payload for quardstrip is (0, 1, 3, 2),
so the PV for quardstrip is c->reg.vertex[2].
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This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
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