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path: root/src/mesa/drivers/dri/i965/brw_sf_state.c
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2010-11-03intel: Annotate debug printout checks with unlikely().Eric Anholt
This provides the optimizer with hints about code hotness, which we're quite certain about for debug printouts (or, rather, while we developers often hit the checks for debug printouts, we don't care about performance while doing so).
2010-10-13Drop GLcontext typedef and use struct gl_context insteadKristian Høgsberg
2010-07-22i965: Respect VS/VP point size result when enabled.Eric Anholt
Fixes glsl-vs-point-size.
2010-06-11i965: GC the last two arguments to brw_cache_data.Eric Anholt
Now that the binding table is streamed indirect state, they were always NULL/0.
2010-06-08intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.Eric Anholt
The new API makes so much more sense, I'd like to forget how the old one worked.
2010-06-08intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.Eric Anholt
The slightly less mechanical change of converting the emit_reloc calls will follow.
2010-04-22i965: Fix scissoring when width or height is 0.Eric Anholt
We would run into trouble due to the hardware using inclusive numbers and the subtraction to handle that producing negative (meaning large positive) coordinates. Bug #27643.
2010-04-21intel: Clean up chipset name and gen num for IronlakeZhenyu Wang
Rename old IGDNG to Ironlake, and set 'gen' number for Ironlake as 5, so tracking the features with generation num instead of special is_ironlake flag. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-01-26intel: Clean up stale comments about cliprects.Eric Anholt
2010-01-25Merge branch 'mesa_7_7_branch'Brian Paul
Conflicts: src/mesa/drivers/dri/intel/intel_screen.c src/mesa/drivers/dri/intel/intel_swapbuffers.c src/mesa/drivers/dri/r300/r300_emit.c src/mesa/drivers/dri/r300/r300_ioctl.c src/mesa/drivers/dri/r300/r300_tex.c src/mesa/drivers/dri/r300/r300_texstate.c
2010-01-22i965: Remove unnecessary headers.Vinson Lee
2010-01-19i965: Allow for variable-sized auxdata in the state cache.Eric Anholt
Everything has been constant-sized until now, but constant buffer handling changes will make us want some additional variable sized array.
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt
Saves ~480 bytes of code.
2009-11-13Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt
2009-11-11i965: fix EXT_provoking_vertex supportRoland Scheidegger
This didn't work for quad/quadstrips at all, and for all other primitive types it only worked when they were unclipped. Fix up the former in gs stage (could probably do without these changes and instead set QuadsFollowProvokingVertexConvention to false), and the rest in clip stage.
2009-11-06i965: Always pass the size argument to brw_cache_data.Eric Anholt
This keeps the individual state files from having to export their structures for brw_state_cache initialization.
2009-08-07i965: Add a note justifying domain choice for the SF VP.Eric Anholt
2009-08-04intel: Add support for EXT_provoking_vertex.Eric Anholt
2009-07-16i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt
2009-07-13i965: add support for new chipsetsXiang, Haihao
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-05-21i956: Make state dependency of SF on drawbuffer bounds match Mesa's.Eric Anholt
Noticed while debugging a weird 1D FBO testcase that left its existing viewport and projection matrix in place when switching drawbuffers. Didn't fix the testcase, though.
2009-04-24i965: fix point size issueRoland Scheidegger
need to clamp point size to user set min/max values, even for constant point size. Fixes glean pointAtten test.
2009-03-24i965: fix point rasterization when rendering to FBORobert Ellison
The FBO pixel coordinate system, with (0,0) as the upper-left pixel, is inverted in Y compared to the normal OpenGL pixel coordinate system, which has (0,0) as its lower-left pixel. Viewport and polygon stipple are sensitive to this inversion; so is point rasterization. The basic fix is simple: when rendering to an FBO, instead of the normal RASTRULE_UPPER_RIGHT that's appropriate for OpenGL windows, use the Y inversion RASTRULE_LOWER_RIGHT. Unfortunately, current Intel documentation has this value listed as "Reserved, but not seen as useful". It does work on at least some i965-class devices, though; and the worst that could happen if an older device didn't support it would be incorrect point rasterization to FBOs, which is what happens already, so this fix is at least no worse than what happens presently, and is better for some (and possibly all) i965-class devices.
2009-03-12i965: move declaration before codeBrian Paul
2009-02-02i965: Remove brw->attribs now that we can just always look in the GLcontext.Eric Anholt
2009-02-02i965: Delete old metaops code now that there are no remaining consumers.Eric Anholt
2009-01-29i965: use bitfields in brw_sf_unit_key structBrian Paul
2009-01-29i965: fix render to FBO/texture orientation bugsBrian Paul
Anytime we're not rendering to the default/window FBO, need to invert rendering, not just when rendering to a texture. Otherwise, if a FBO consists of a mix of textures and renderbuffers the up/down orientation was inconsistant. Fixes shadowtex.c bad rendering.
2009-01-26i965: scissor rect was inverted when rendering to textureBrian Paul
2009-01-16i965: fix polygon culling bug when rendering to a texture/FBOBrian Paul
Since we use an inverted viewport transformation for render to texture, that inverts front/back polygon orientation. Now glCullFace(GL_FRONT / GL_BACK) works correctly.
2009-01-11replace nearbyint() by rint() for now.Matthieu Herrb
2008-11-12i965: Fix up SF max_threads.Eric Anholt
We were dividing the number of URB entries by two to get number of threads, which looks suspiciously like a copy'n'paste-o from brw_vs_state.c. Also, the maximum number of threads is 24, not 12.
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul
Makefile.template
2008-09-10intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.Eric Anholt
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-08intel-gem: Update to new check_aperture API for classic mode.Eric Anholt
To do this, I had to clean up some of 965 state upload stuff. We may end up over-emitting state in the aperture overflow case, but that should be rare, and I'd rather have the simplification of state management.
2008-06-11[intel-gem] Chase domain flag renaming in the DRM.Eric Anholt
This is an API breakage only.
2008-06-03[intel] Convert drivers to using libdrm bufmgr code.Eric Anholt
2008-05-07GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.Eric Anholt
The GEM flags are much more descriptive for what we need. Since this makes bufmgr_fake rather device-specific, move it to the intel common directory. We've wanted to do device-specific stuff to it before.
2008-04-18i965: initial attempt at fixing the aperture overflowDave Airlie
Makes state emission into a 2 phase, prepare sets things up and accounts the size of all referenced buffer objects. The emit stage then actually does the batchbuffer touching for emitting the objects. There is an assert in dri_emit_reloc if a reloc occurs for a buffer that hasn't been accounted yet.
2008-03-17[i965] round pointsize to nearest int according to specZou Nan hai
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2008-01-06Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.Brian
These fields are no longer indexed by shader output. Now, we just have a simple array of renderbuffer pointers. If the shader writes to gl_FragData[i], send those colors to the N _ColorDrawBuffers. Otherwise, replicate the single gl_FragColor (or the fixed-function color) to the N _ColorDrawBuffers. A few more changes and simplifications can follow from this...
2008-01-03[intel] Convert relocations to not be cleared out on buffer submit.Eric Anholt
We have two consumers of relocations. One is static state buffers, which want the same relocation every time. The other is the batchbuffer, which gets thrown out immediately after submit. This lets us reduce repeated computation for static state buffers, and clean up the code by moving relocations nearer to where the state buffer is computed.
2008-01-02[965] Convert SF unit to use a cache key instead of brw_cache_data.Eric Anholt
2007-12-20[965] Enable EXT_framebuffer_object.Eric Anholt
To do so, merge the remainnig necessary code from the buffers, blit, span, and screen code to shared, and replace it with those.
2007-12-17[965] Simplify scissor handling by using DrawBuffer values.Eric Anholt
2007-12-17[965] Replace our own depth constants in intel context with GL context ones.Eric Anholt
2007-12-14[965] Replace the state cache suballocator with direct dri_bufmgr use.Eric Anholt
The user-space suballocator that was used avoided relocation computations by using the general and surface state base registers and allocating those types of buffers out of pools built on top of single buffer objects. It also avoided calls into the buffer manager for these small state allocations, since only one buffer object was being used. However, the buffer allocation cost appears to be low, and with relocation caching, computing relocations for buffers is essentially free. Additionally, implementing the suballocator required a don't-fence-subdata flag to disable waiting on buffer maps so that writing new data didn't block on rendering using old data, and careful handling when mapping to update old data (which we need to do for unavoidable relocations with FBOs). More importantly, when the suballocator filled, it had no replacement algorithm and just threw out all of the contents and forced them to be recomputed, which is a significant cost. This is the first step, which just changes the buffer type, but doesn't yet improve the hash table to not result in full recompute on overflow. Because the buffers are all allocated out of the general buffer allocator, we can no longer use the general/surface state bases to avoid relocations, and they are set to 0 instead.