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path: root/src/mesa/drivers/dri/i965/brw_tex_layout.c
AgeCommit message (Collapse)Author
2010-01-30i965: Remove unnecessary headers.Vinson Lee
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt
Saves ~480 bytes of code.
2009-10-23intel: Keep track of x,y offsets in miptrees and use them for blitting.Eric Anholt
By just using offsets, we confused the hardware's tiling calculations, resulting in failures in miptree validation and blit clears. Fixes piglit fbo-clearmipmap. Bug #23552. (automatic mipmap generation)
2009-08-19intel: Fix failure to commit -a --amend before last push.Eric Anholt
2009-08-19intel: Align cubemap texture height to its padding requirements.Eric Anholt
2009-08-13i965: fix cube map on IGDNGXiang, Haihao
2009-07-13i965: add support for new chipsetsXiang, Haihao
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-06-17i965: Fix up texture layout for small things with wide pitches (tiled)Eric Anholt
We were packing according to the pitch, while the hardware appears to base it on the base level width. With this and the previous commit, fbo-cubemap now matches untiled behavior.
2009-06-04intel: Add support for tiled textures.Eric Anholt
This is about a 30% performance win in OA with high settings on my GM45, and experiments with 915GM indicate that it'll be around a 20% win there. Currently, 915-class hardware is seriously hurt by the fact that we use fence regs to control the tiling even for 3D instructions that could live without them, so we spend a bunch of time waiting on previous rendering in order to pull fences off. Thus, the texture_tiling driconf option defaults off there for now.
2009-05-21i965: fix whitespace in brw_tex_layout.cEric Anholt
The broken indentation was driving me crazy, so fix other stuff while I'm here.
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul
Makefile.template
2007-12-18[INTEL] Fix 965 to use new centralized mipmap pitch functionKeith Packard
2007-12-07[965] Convert the driver to dri_bufmgr interface and enable TTM.Eric Anholt
This is currently believed to work but be a significant performance loss. Performance recovery should be soon to follow. The dri_bo_fake_disable_backing_store() call was added to allow backing store disable like bufmgr_fake.c did, which is a significant performance win (though it's missing the no-fence-subdata part). This commit is a squash merge of the 965-ttm branch, which had some history I wanted to avoid pulling due to noisiness and brokenness at many points for git-bisecting.
2007-11-19[965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.Eric Anholt
2007-10-04[965] Replace various alignment code with a shared ALIGN() macro.Eric Anholt
In the process, fix some alignment issues: - Scratch space allocation was aligned into units of 1KB, while the allocation wanted units of bytes, so we never allocated enough space for scratch. - GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
2007-08-17i965: align width/height for volume textureXiang, Haihao
2006-12-14Share code to lay out >= 945 style 2D mipmaps between i915tex and i965 drivers.Michel Dänzer
Use the i965 version as it has some fixes over the i915tex version.
2006-09-20Support ARB_texture_rectangle.Keith Whitwell
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.