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path: root/src/mesa/drivers/dri/i965/brw_urb.c
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2010-04-21intel: Clean up chipset name and gen num for IronlakeZhenyu Wang
Rename old IGDNG to Ironlake, and set 'gen' number for Ironlake as 5, so tracking the features with generation num instead of special is_ironlake flag. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-02-19Replace the _mesa_*printf() wrappers with the plain libc versionsKristian Høgsberg
2009-12-22intel: Replace IS_G4X() across the driver with context structure usage.Eric Anholt
Saves ~2KB of code.
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt
Saves ~480 bytes of code.
2009-07-13i965: add support for new chipsetsXiang, Haihao
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-06-30i965: Increase G4X default VS URB allocation to actually allow 32 threads.Eric Anholt
This improves the performance of my GLSL demo by 30%. It also fixes the VS deadlock that ut2004 had, for reasons I can't explain. Bug #21330.
2008-11-12i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads.Eric Anholt
The clip thread could potentially deadlock when processing tristrips since being moved back to dual-thread mode, as the two threads could each have 4 VUEs referenced and not be able to allocate another one since SF processing wasn't able to continue (needing 5 entries before it freed 2). In constrained URB mode, similar deadlock could even have occurred with polygons (so we cut back max_threads if we can't handle it any primitive type).
2008-11-12i965: Add a big comment explaining my understanding of URB management.Eric Anholt
It shouldn't offer anything new over what's in the docs (except for G4X notes), but here it's all in one place.
2008-11-02i965: Fix copy'n'paste issue that made brw->urb.constrained useless.Eric Anholt
Also, add a comment explaining what brw->urb.constrained tries to do.
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-08intel-gem: Update to new check_aperture API for classic mode.Eric Anholt
To do this, I had to clean up some of 965 state upload stuff. We may end up over-emitting state in the aperture overflow case, but that should be rare, and I'd rather have the simplification of state management.
2008-08-08965: cleanups to state emission from aperture checking and state ordering.Eric Anholt
2008-04-22 [i965] This is to fix random crash in some maps of Ut2004 demo.Zou Nan hai
e.g. bridge of fate. If vs output is big, driver may fall back to use 8 urb entries for vs, unfortunally, for some unknown reason, if vs is working at 4x2 mode, 8 entries is not enough, may lead to gpu hang.
2008-04-18i965: initial attempt at fixing the aperture overflowDave Airlie
Makes state emission into a 2 phase, prepare sets things up and accounts the size of all referenced buffer objects. The emit stage then actually does the batchbuffer touching for emitting the objects. There is an assert in dri_emit_reloc if a reloc occurs for a buffer that hasn't been accounted yet.
2008-02-14i965: remove unused hal hooksDave Airlie
These don't appear to have ever been used.
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2007-03-25i965: The given urb layout(maximal size of urb entries and theXiang, Haihao
values for nr of entries) should meet the requirement.
2006-09-14VS nr of urb entries is constrained to be one of a fixed set of values,Keith Whitwell
specifically {8,16,32}.
2006-09-12Potential fix for doom3 lockups. Seems that there is a conflictKeith Whitwell
between the vertex cache, the vertex shader and the clipping stages, all of which are competitors for URB entries assigned to the VS unit. This change reduces the maximum number of clip and VS threads by enough to ensure that they cannot consume all the available URB entries, and then reduces the number somewhat more up to an arbitary amount I discovered by trial and error. Unfortunately trial and error solutions don't inspire total confidence...
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.