| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-04-17 | i915: fix broken indirect constant buffer reads | Brian Paul | |
| The READ message's msg_control value can be 0 or 1 to indicate that the Oword should be read into the lower or upper half of the target register. It seems that the other half of the register gets clobbered though. So we read into two dest registers then use a MOV to combine the upper/lower halves. | |||
| 2009-04-17 | i965: updated CURBE allocation code | Brian Paul | |
| Now that we have real constant buffers, the demands on the CURBE are lessened. When we use real VS/WM constant buffers we only use the CURBE for clip planes. | |||
| 2009-04-16 | Merge branch 'register-negate' | Brian Paul | |
| 2009-04-16 | i965: implement relative addressing for VS constant buffer reads | Brian Paul | |
| A scatter-read should be possible, but we're just using two READs for the time being. | |||
| 2009-04-16 | i965: handle address reg in get_dst() | Brian Paul | |
| 2009-04-16 | i965: fix const buffer temp register clobbering | Brian Paul | |
| Calls to release_tmps() were causing the temps holding constants to get recycled. | |||
| 2009-04-14 | mesa: merge the prog_src_register::NegateBase and NegateAbs fields | Brian Paul | |
| There's really no need for two negation fields. This came from the GL_NV_fragment_program extension. The new, unified Negate bitfield applies after the absolute value step. | |||
| 2009-04-14 | i965: fix VS constant buffer reads | Brian Paul | |
| This mostly came down to finding the right MRF incantation in the brw_dp_READ_4_vs() function. Note: this feature is still disabled (but getting close to done). | |||
| 2009-04-14 | i965: checkpoint commit: VS constant buffers | Brian Paul | |
| Hook up a constant buffer, binding table, etc for the VS unit. This will allow using large constant buffers with vertex shaders. The new code is disabled at this time (use_const_buffer=FALSE). | |||
| 2009-04-03 | i965: formatting clean-ups | Brian Paul | |
| 2009-04-03 | i965: whitespace changes, comments | Brian Paul | |
| 2009-03-13 | i965: debug code, use gl_register_file type | Brian Paul | |
| 2009-02-13 | i965: rewrite the code for handling shader subroutine calls | Brian Paul | |
| Previously, the prog_instruction::Data field was used to map original Mesa instructions to brw instructions in order to resolve subroutine calls. This was a rather tangled mess. Plus it's an obstacle to implementing dynamic allocation/growing of the instruction buffer (it's still a fixed size). Mesa's GLSL compiler emits a label for each subroutine and CAL instruction. Now we use those labels to patch the subroutine calls after code generation has been done. We just keep a list of all CAL instructions that needs patching and a list of all subroutine labels. It's a simple matter to resolve them. This also consolidates some redundant post-emit code between brw_vs_emit.c and brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data fields at the end. Plus, a bunch of new comments. | |||
| 2009-02-13 | i965: add missing break for OPCODE_RET case | Brian Paul | |
| This doesn't effect correctness, but we were emitting an extraneous ADD. | |||
| 2009-02-02 | i965: Delete old metaops code now that there are no remaining consumers. | Eric Anholt | |
| 2009-01-21 | i965: Remove gratuitous whitespace in INTEL_DEBUG=wm output. | Eric Anholt | |
| 2009-01-07 | i965: Note when we drop saturate mode on the floor in a VP. | Eric Anholt | |
| 2009-01-07 | i965: Add support for LRP in VPs. | Eric Anholt | |
| Bug #19226. | |||
| 2009-01-05 | i965: implement OPCODE_TRUNC (round toward zero) on vertex path. | Brian Paul | |
| Also, fix some RNDD vs. RNDZ confusion elsewhere. | |||
| 2009-01-01 | i965: fix comment | Brian Paul | |
| 2009-01-01 | i965: implement OPCODE_NRM3/NRM4 | Brian Paul | |
| 2009-01-01 | i965: whitespace, comment changes | Brian Paul | |
| 2008-12-19 | 965 / GLSL: Use full precision for EXP instruction | Ian Romanick | |
| The partial precision mode doesn't have quite enough bits of precision to pass conformance tests. | |||
| 2008-11-02 | i965: Clean up stale NDC comment. | Eric Anholt | |
| 2008-11-02 | i965: Avoid vs header computation for negative rhw on G4X. | Eric Anholt | |
| This cuts one MOV out when setting a zero header. | |||
| 2008-11-02 | i965: Merge GM45 into the G4X chipset define. | Eric Anholt | |
| The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up. | |||
| 2008-09-25 | i965: support for sin() and cos() in vertex shaders. | Sam Hocevar | |
| 2008-09-25 | i965: more meaningful message for unsupported opcodes. | Sam Hocevar | |
| 2008-08-21 | 965: Fix color clamping issues | Krzysztof Czurylo | |
| Patch is correctly applied this time. | |||
| 2008-08-21 | Formatting changes to ease application of patches | Ian Romanick | |
| 2008-07-24 | Revert "965: Fix color clamping issues" | Ian Romanick | |
| This reverts commit b993d539a76e7f1446890a85e4b61deec4d4162d. The patch was applied incorrectly. Actual fix coming soon. Sorry for the noise. | |||
| 2008-07-21 | 965: Fix color clamping issues | Pawel Pieczul | |
| 2008-07-08 | i965: official name for GM45 chipset | Xiang, Haihao | |
| 2008-04-17 | Revert "[i965] renable regative rhw test" | Xiang, Haihao | |
| This reverts commit 3158e981f5f37768e9b04765704b9eaece8b899b. rhw issue has gone away on IGD. | |||
| 2008-01-31 | [i965] renable regative rhw test | Zou Nan hai | |
| 2008-01-29 | i965: new integrated graphics chipset support | Xiang, Haihao | |
| 2008-01-16 | [965] Fix inversion of SLT/SGE results in vertex programs. | Eric Anholt | |
| The WM code had this right, so copy its behavior. This reverts a flipping of the arguments to SLT in brw_vs_tnl which came in with the GLSL code that probably occurred to work around the flipped results, and brings the code back in line with t_vp_build.c. | |||
| 2007-12-29 | fix fd.o bug #13847 | Zou Nan hai | |
| 2007-10-26 | Merge branch '965-glsl' | Zou Nan hai | |
| Conflicts: src/mesa/drivers/dri/i965/brw_sf.h src/mesa/drivers/dri/i965/intel_context.c | |||
| 2007-09-18 | fix double free in 965-glsl branch | Zou Nan hai | |
| 2007-09-11 | Fix-up #includes to remove some -I options. | Brian | |
| eg: #include "shader/program.h" and remove -I$(TOP)/src/mesa/program | |||
| 2007-08-02 | Fix typo in logic for unalias2() | Keith Whitwell | |
| 2007-07-04 | fix issue with output as src register. | Zou Nan hai | |
| 2007-07-03 | Fix a nasty bug... | Zou Nan hai | |
| 2007-06-21 | support branch and loop in pixel shader | Zou Nan hai | |
| most of the sample working with some small modification | |||
| 2007-05-09 | Support loop, conditional update fix | Zou Nan hai | |
| 2007-04-30 | support nested function call | Zou Nan hai | |
| else instruction fix. | |||
| 2007-04-12 | Initial 965 GLSL support | Zou Nan hai | |
| 2007-02-23 | Update DRI drivers for new glsl compiler. | Brian | |
| Mostly: - update #includes - update STATE_* token code | |||
| 2006-10-31 | cleanup code, compiles with vbo changes | Keith Whitwell | |
 |
index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
| summaryrefslogtreecommitdiff |