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path: root/src/mesa/drivers/dri/i965/brw_vs_emit.c
AgeCommit message (Collapse)Author
2009-05-08i965: const qualifiersBrian Paul
2009-05-07i965: relAddr local var (to make debug/test a little easier)Brian Paul
2009-05-01Merge branch 'const-buffer-changes'Brian Paul
Conflicts: src/mesa/drivers/dri/i965/brw_curbe.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/i965/brw_wm_glsl.c
2009-04-27i965: only upload constant buffer data when we actually need the const bufferBrian Paul
Make the use_const_buffer field per-program and only call the code which updates the constant buffer's data if the flag is set. This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052 (cherry picked from master, commit dc9705d12d162ba6d087eb762e315de9f97bc456)
2009-04-27i965: only upload constant buffer data when we actually need the const bufferBrian Paul
Make the use_const_buffer field per-program and only call the code which updates the constant buffer's data if the flag is set. This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052
2009-04-22i965: disable debug printfBrian Paul
2009-04-22i965: enable VS constant buffersBrian Paul
In the VS constants can now be handled in two different ways: 1. If there's room in the GRF, put constants there. They're preloaded from the CURBE prior to VS execution. This is the historical approach. The problem is the GRF may not have room for all the shader's constants and temps and misc registers. Hence... 2. Use a separate constant buffer which is read from using a READ message. This allows a very large number of constants and frees up GRF regs for shader temporaries. This is the new approach. May be a little slower than 1. 1 vs. 2 is chosen according to how many constants and temps the shader needs.
2009-04-17i915: fix broken indirect constant buffer readsBrian Paul
The READ message's msg_control value can be 0 or 1 to indicate that the Oword should be read into the lower or upper half of the target register. It seems that the other half of the register gets clobbered though. So we read into two dest registers then use a MOV to combine the upper/lower halves.
2009-04-17i965: updated CURBE allocation codeBrian Paul
Now that we have real constant buffers, the demands on the CURBE are lessened. When we use real VS/WM constant buffers we only use the CURBE for clip planes.
2009-04-16Merge branch 'register-negate'Brian Paul
2009-04-16i965: implement relative addressing for VS constant buffer readsBrian Paul
A scatter-read should be possible, but we're just using two READs for the time being.
2009-04-16i965: handle address reg in get_dst()Brian Paul
2009-04-16i965: fix const buffer temp register clobberingBrian Paul
Calls to release_tmps() were causing the temps holding constants to get recycled.
2009-04-14mesa: merge the prog_src_register::NegateBase and NegateAbs fieldsBrian Paul
There's really no need for two negation fields. This came from the GL_NV_fragment_program extension. The new, unified Negate bitfield applies after the absolute value step.
2009-04-14i965: fix VS constant buffer readsBrian Paul
This mostly came down to finding the right MRF incantation in the brw_dp_READ_4_vs() function. Note: this feature is still disabled (but getting close to done).
2009-04-14i965: checkpoint commit: VS constant buffersBrian Paul
Hook up a constant buffer, binding table, etc for the VS unit. This will allow using large constant buffers with vertex shaders. The new code is disabled at this time (use_const_buffer=FALSE).
2009-04-03i965: formatting clean-upsBrian Paul
2009-04-03i965: whitespace changes, commentsBrian Paul
2009-03-13i965: debug code, use gl_register_file typeBrian Paul
2009-02-13i965: rewrite the code for handling shader subroutine callsBrian Paul
Previously, the prog_instruction::Data field was used to map original Mesa instructions to brw instructions in order to resolve subroutine calls. This was a rather tangled mess. Plus it's an obstacle to implementing dynamic allocation/growing of the instruction buffer (it's still a fixed size). Mesa's GLSL compiler emits a label for each subroutine and CAL instruction. Now we use those labels to patch the subroutine calls after code generation has been done. We just keep a list of all CAL instructions that needs patching and a list of all subroutine labels. It's a simple matter to resolve them. This also consolidates some redundant post-emit code between brw_vs_emit.c and brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data fields at the end. Plus, a bunch of new comments.
2009-02-13i965: add missing break for OPCODE_RET caseBrian Paul
This doesn't effect correctness, but we were emitting an extraneous ADD.
2009-02-02i965: Delete old metaops code now that there are no remaining consumers.Eric Anholt
2009-01-21i965: Remove gratuitous whitespace in INTEL_DEBUG=wm output.Eric Anholt
2009-01-07i965: Note when we drop saturate mode on the floor in a VP.Eric Anholt
2009-01-07i965: Add support for LRP in VPs.Eric Anholt
Bug #19226.
2009-01-05i965: implement OPCODE_TRUNC (round toward zero) on vertex path.Brian Paul
Also, fix some RNDD vs. RNDZ confusion elsewhere.
2009-01-01i965: fix commentBrian Paul
2009-01-01i965: implement OPCODE_NRM3/NRM4Brian Paul
2009-01-01i965: whitespace, comment changesBrian Paul
2008-12-19965 / GLSL: Use full precision for EXP instructionIan Romanick
The partial precision mode doesn't have quite enough bits of precision to pass conformance tests.
2008-11-02i965: Clean up stale NDC comment.Eric Anholt
2008-11-02i965: Avoid vs header computation for negative rhw on G4X.Eric Anholt
This cuts one MOV out when setting a zero header.
2008-11-02i965: Merge GM45 into the G4X chipset define.Eric Anholt
The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
2008-09-25i965: support for sin() and cos() in vertex shaders.Sam Hocevar
2008-09-25i965: more meaningful message for unsupported opcodes.Sam Hocevar
2008-08-21965: Fix color clamping issuesKrzysztof Czurylo
Patch is correctly applied this time.
2008-08-21Formatting changes to ease application of patchesIan Romanick
2008-07-24Revert "965: Fix color clamping issues"Ian Romanick
This reverts commit b993d539a76e7f1446890a85e4b61deec4d4162d. The patch was applied incorrectly. Actual fix coming soon. Sorry for the noise.
2008-07-21965: Fix color clamping issuesPawel Pieczul
2008-07-08i965: official name for GM45 chipsetXiang, Haihao
2008-04-17Revert "[i965] renable regative rhw test"Xiang, Haihao
This reverts commit 3158e981f5f37768e9b04765704b9eaece8b899b. rhw issue has gone away on IGD.
2008-01-31[i965] renable regative rhw testZou Nan hai
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2008-01-16[965] Fix inversion of SLT/SGE results in vertex programs.Eric Anholt
The WM code had this right, so copy its behavior. This reverts a flipping of the arguments to SLT in brw_vs_tnl which came in with the GLSL code that probably occurred to work around the flipped results, and brings the code back in line with t_vp_build.c.
2007-12-29fix fd.o bug #13847Zou Nan hai
2007-10-26Merge branch '965-glsl'Zou Nan hai
Conflicts: src/mesa/drivers/dri/i965/brw_sf.h src/mesa/drivers/dri/i965/intel_context.c
2007-09-18fix double free in 965-glsl branchZou Nan hai
2007-09-11Fix-up #includes to remove some -I options.Brian
eg: #include "shader/program.h" and remove -I$(TOP)/src/mesa/program
2007-08-02Fix typo in logic for unalias2()Keith Whitwell
2007-07-04 fix issue with output as src register.Zou Nan hai