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Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
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We were returning the negative absolute value, instead of the absolute
value. Fixes glsl-vs-abs-neg.
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In general, we have to negate in immediate values we pass in because
the src1 negate field in the register description is in the bits3 slot
that the 32-bit value is loaded into, so it's ignored by the hardware.
However, the src0 negate field is in bits1, so after we'd negated the
immediate value loaded in, it would also get negated through the
register description. This broke this VP instruction in the position
calculation in civ4:
MAD TEMP[1], TEMP[1], CONST[256].zzzz, CONST[256].-y-y-y-y;
Bug #30156
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This fixes
brw_eu_emit.c:179: validate_reg: Assertion `width == 1' failed.
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RNDD isn't one of the instructions that can do conversion from
execution type to destination type.
Fixes glsl-vs-arrays-3.
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VS places color attributes together so that SF unit can fetch the right
attribute according to object orientation. This fixes light issue in
mesa demo geartrain, projtex.
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Last minute change for gen6 with 0 used params dropped the multiply.
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This eases the gen6 implementation, which can only handle up to 32
registers of constants, while likely not penalizing real apps using
reladdr since all of those I've seen also end up hitting the pull
constant buffer. On gen6, the constant map means that simple NV VPs
fit under the 32-reg limit and now succeed. Fixes around 10 testcases.
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gen6 builtin RSQ apparently clamps negative values to 0 instead of
returning the RSQ of the absolute value like ARB_fragment_program
desires and pre-gen6 apparently does.
Fixes:
glean/fp1-RSQ test 2 (reciprocal square root of negative value)
glean/vp1-RSQ test 2 (reciprocal square root of negative value)
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This follows the changes done for the FS alongside the EU emit code.
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Like Eric's workaround patch of commit 490c23ee6be2e8531b5a14d42f808de83d401130.
This forces to align1 mode for math2 too.
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https://bugs.freedesktop.org/show_bug.cgi?id=31894
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Cuts the extra CMP instruction that used to precede SEL.
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Sometimes we swizzled in a different channel it looked like, and
sometimes we swizzled in zero. Or something.
Having looked at the output of another code generator for this chip,
this is approximately what they do, too: use align1 math on
temporaries, and then move the results into place.
Fixes:
glean/vp1-EX2 test
glean/vp1-EXP test
glean/vp1-LG2 test
glean/vp1-RCP test (reciprocal)
glean/vp1-RSQ test 1 (reciprocal square root)
shaders/glsl-cos
shaders/glsl-sin
shaders/glsl-vs-masked-cos
shaders/vpfp-generic/vp-exp-alias
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This reverts commit 9c39a9fcb2c76897e9b5aff68ce197a411c4e25c.
Remove VS SPF mode, conditional instruction works for VS now.
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This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
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Fixes piglit user-clip, and compiz desktop switching when dragging a
window and using just 2 desktops. Bug #30446.
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There was code to do this for pre-gen6 already, this just enables it
for gen6 as well.
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Until conditional instructions were fixed, use SPF mode instead for now.
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Don't double store position in vertex attribute. This makes color
interpolation right by using barycentric coordinates.
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We carefully multiplied our two ints (since we want to be precise
after all) then stored them in a float, which is not specced to really
work, in addition to wasting precision. Fixes
vp-arl-constant-array-huge-* things since the assertions were added.
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This is a requirement specified in the docs. No behavior change in
glsl-vs-varying-array.shader_test that violated these requirements.
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Fixes the 7 regressions with constant buffers forced on with piglit -t
glsl (glsl-vs-if-*).
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We always need to set it, so pass it in.
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Fixes: glsl-vs-varying-array
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Whenever the accumulator results are needed, this bit must be set.
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Otherwise, we might end up with the if stack pointing at the wrong
place. Fixes GPU hang with glsl-vs-if-loop.
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Fixes glsl-vs-if-nested (70.0 is not <= 70.000648 thanks to the
swizzle bits getting set). Some safety checks are added to make sure
this doesn't happen again as we increase the usage of immediate values
in program generation.
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Fixes glsl-vs-dot-vec2.
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Mixing stderr (_mesa_print_program, _mesa_print_instruction,
_mesa_print_alu) with stdout means that when writing both to a file,
there isn't a consistent ordering between the two.
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This pulls in multiple i965 driver fixes which will help ensure better
testing coverage during development, and also gets past the conflicts
of the src/mesa/shader -> src/mesa/program move.
Conflicts:
src/mesa/Makefile
src/mesa/main/shaderapi.c
src/mesa/main/shaderobj.h
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Clarifies program assembly, and with a little tweak to always use
constant_map, we could cut down on constant buffer payload.
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Fixes glsl-vs-arrays. Bug #27388.
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The ARL value is increments of vec4 in the register file. But
PROGRAM_TEMPORARY or PROGRAM_INPUT are stored as vec4s interleaved
between the two verts being executed (thus a vec8 each), compared to
PROGRAM_STATE_VAR being packed vec4s.
Fixes:
glsl-vs-arrays-2
glsl-vs-mov-after-deref
(without regressing glsl-vs-arrays-3)
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The previous support was overly complicated by trying to use the same
1-OWORD message for both offsets.
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To quiet a compiler warning.
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There was confusion on both the size of message we can send, and on
what the URB destination offset means.
The remaining problems appear to be due to spilling of regs in the
fragment shader being broken.
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The old compiler didn't use SSG, and instead emitted SGT/SGT/SUB. We
can do a little better for SSG than we do for the SGT series.
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