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path: root/src/mesa/drivers/dri/i965/brw_wm_emit.c
AgeCommit message (Collapse)Author
2009-12-31Merge branch 'mesa_7_7_branch'Brian Paul
Conflicts: configs/darwin src/gallium/auxiliary/util/u_clear.h src/gallium/state_trackers/xorg/xorg_exa_tgsi.c src/mesa/drivers/dri/i965/brw_draw_upload.c
2009-12-28intel: Silence compiler warnings.Vinson Lee
2009-12-22intel: Replace IS_G4X() across the driver with context structure usage.Eric Anholt
Saves ~2KB of code.
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt
Saves ~480 bytes of code.
2009-11-13i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
This should fix TXB on G45 and older in the GLSL case.
2009-11-13i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c.Eric Anholt
New comments should explain some of the confusion about how this message works.
2009-11-13i965: Clean up emit_tex a bit.Eric Anholt
2009-11-13Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt
2009-11-13i965: Clean up Ironlake sampler type definitions.Eric Anholt
They're the same regardless of execution width for 8, 4x2, and 16.
2009-11-12i965: Fix Ironlake shadow comparisons.Eric Anholt
The cube map array index arg is always present.
2009-11-06i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt
No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size.
2009-11-06i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
2009-11-06i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
This should fix issues with antialiased lines in GLSL.
2009-11-06i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst.
2009-11-06i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt
2009-11-06i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt
2009-11-06i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt
This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
2009-09-11i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.Eric Anholt
Previously, it was trying to mess around with the varying's WM setup data to produce a result. Along with not actually working when passed a varying, this wouldn't work if you did dFd[xy]() on a temporary. Instead, just calculate the derivative using the neighbors in the subspan.
2009-09-04i965: Add support for KIL_NV in brw_wm_emit.cEric Anholt
I ran into this lack of support when writing a shader that always discarded the fragments.
2009-08-26i965: clean up texture target switchesBrian Paul
2009-08-22i965: Implement frag prog DPH like DP4Ian Romanick
DPH can output to any component, not just to X. This allows fpalu.c to run without hitting the assertion in emit_dph.
2009-08-12i965: Handle scalar result swizzling in shared GLSL/non-GLSL code.Eric Anholt
This is preparation for merging of brw_wm_glsl.c and brw_wm_emit.c, and glsl.c doesn't swizzle channel results around.
2009-08-12i965: Remove some unused WM opcode args.Eric Anholt
2009-08-04i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out, and running intel-gen4disasm on it.
2009-07-13i965: add support for new chipsetsXiang, Haihao
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-02i965: fixes for JMPIXiang, Haihao
1. the data type of <src1> (JMPI offset) must be D 2. execution size must be 1 3. NoMask 4. instruction compression isn't allowed.
2009-06-26i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger
the driver used to overwrite grf0 then use implicit move by send instruction to move contents of grf0 to mrf1. However, we must not overwrite grf0 since it's still used later for fb write. Instead, do the move directly do mrf1 (we could use implicit move from another grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't seem to make sense). I think the dp_READ/WRITE_16 functions may suffer from the same issue. While here also remove unnecessary msg_reg_nr parameter from the dataport functions since always message register 1 is used.
2009-06-02i965: Support OPCODE_TRUNC in the brw_wm_fp.c code.Eric Anholt
This gets two more glean glsl1 tests using the non-GLSL path.
2009-04-09i965: new SURF_INDEX_ macrosBrian Paul
Used to map drawables, textures and constant buffers to surface binding table indexes.
2009-04-03i965: comments, whitespace changesBrian Paul
2009-03-23i965: Fix glFrontFacing in twoside GLSL demo.Eric Anholt
This also cuts instructions by just using the existing bit in the payload rather than computing it from the determinant in the SF unit and passing it as a varying down to the WM. Something still goes wrong with getting the backface color right, but a simpler shader appears to get the right result.
2009-03-12i965: commentsBrian Paul
2009-02-20i965: use the new prog_instruction::TexShadow fieldBrian Paul
GLSL shadow() sampler calls are properly propogated down to the driver now. The glean glsl1 shadow() tests work (except for the alpha channel).
2009-01-01i965: indentation and formatting fixesBrian Paul
2008-09-25i965: more meaningful message for unsupported opcodes.Sam Hocevar
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul
Makefile.template
2008-07-23965: Fix partially transparent textures in Doom 3 engine gamesPawel Pieczul
Numbers of destination depth registers corrected (destination stencil register was sent as depth register).
2008-06-21replace __inline and __inline__ with INLINE macroBrian Paul
2008-04-22i965: fix DEPTH_TEXTURE_MODE (bug #14220)Xiang, Haihao
2008-03-21[965] Avoid emitting dead code for DPx/math instructions.Michal Wajdeczko
The pass1 optimization stage clears out writemasks and registers, but the instructions themselves are still being processed at this stage, and could have resulted in them still being emitted.
2008-03-21[965] Improve pinterp performance by delaying reads of just-written regs.Michal Wajdeczko
2008-03-21[965] Fix negating of unsigned value in emit_wpos_xy.Michal Wajdeczko
2008-03-17 [i965] fix wpos height 1 pixel higherZou Nan hai
2008-03-13 [i965] multiple rendering target supportZou Nan hai
2008-02-28[965] Bug #9151: make fragment.position return window coords not screen coords.Eric Anholt
2007-11-30i965: use uncompressed instruction to ensure onlyXiang, Haihao
Pixel Mask Copy is modified as the pixel shader thread turns off pixels based on kill instructions.
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