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path: root/src/mesa/drivers/dri/i965/brw_wm_emit.c
AgeCommit message (Collapse)Author
2008-04-22i965: fix DEPTH_TEXTURE_MODE (bug #14220)Xiang, Haihao
2008-03-21[965] Avoid emitting dead code for DPx/math instructions.Michal Wajdeczko
The pass1 optimization stage clears out writemasks and registers, but the instructions themselves are still being processed at this stage, and could have resulted in them still being emitted.
2008-03-21[965] Improve pinterp performance by delaying reads of just-written regs.Michal Wajdeczko
2008-03-21[965] Fix negating of unsigned value in emit_wpos_xy.Michal Wajdeczko
2008-03-17 [i965] fix wpos height 1 pixel higherZou Nan hai
2008-03-13 [i965] multiple rendering target supportZou Nan hai
2008-02-28[965] Bug #9151: make fragment.position return window coords not screen coords.Eric Anholt
2007-11-30i965: use uncompressed instruction to ensure onlyXiang, Haihao
Pixel Mask Copy is modified as the pixel shader thread turns off pixels based on kill instructions.
2007-10-09 shadow sampler fix.Zou Nan hai
1. spec requite result (0, 0, 0, 1) instead of (0, 0, 0, 0) 2. support shadow sampler in simd8
2007-06-21 support branch and loop in pixel shaderZou Nan hai
most of the sample working with some small modification
2007-04-12 Initial 965 GLSL supportZou Nan hai
2007-02-23Update DRI drivers for new glsl compiler.Brian
Mostly: - update #includes - update STATE_* token code
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.