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path: root/src/mesa/drivers/dri/i965/brw_wm_glsl.c
AgeCommit message (Expand)Author
2010-02-19Replace the _mesa_*printf() wrappers with the plain libc versionsKristian Høgsberg
2009-12-31Merge branch 'mesa_7_7_branch'Brian Paul
2009-12-28intel: Silence compiler warnings.Vinson Lee
2009-12-26i965: Extra asserts on flow control instructions to clarify for clang.Eric Anholt
2009-12-26i965: Clean up double initialization of dst_flags from a rebase resolve.Eric Anholt
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt
2009-11-17Merge branch 'outputswritten64'Ian Romanick
2009-11-13i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
2009-11-13i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c.Eric Anholt
2009-11-13i965: Clean up Ironlake sampler type definitions.Eric Anholt
2009-11-06i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
2009-11-06i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt
2009-11-06i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt
2009-11-06i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt
2009-11-06i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt
2009-11-06i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt
2009-11-06i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt
2009-11-06i965: Collect GLSL src/dst regs up in generic code.Eric Anholt
2009-10-29i965: use macros to get/set prog_instruction::Aux fieldBrian Paul
2009-09-11i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.Eric Anholt
2009-08-26i965: fix incorrect tex unit in emit_tex() and emit_txb()Brian Paul
2009-08-26i965: clean-up tex target switchesBrian Paul
2009-08-25i965: add some texture unit/target assertionsBrian Paul
2009-08-12i965: Allocate destination registers for GLSL TEX instructions contiguously.Eric Anholt
2009-08-12i965: drop dead scalar handling in GLSL.Eric Anholt
2009-08-12i965: Drop GLSL ABS code, which is translated away in brw_wm_fp.Eric Anholt
2009-08-12i965: Drop code for emitting OPCODE_SUB, since brw_wm_fp.c makes it an ADD.Eric Anholt
2009-08-12i965: Handle scalar result swizzling in shared GLSL/non-GLSL code.Eric Anholt
2009-08-12i965: Flag ARL-using programs as requiring brw_wm_glsl.cEric Anholt
2009-08-04i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt
2009-07-31Rename TGSI LOOP instruction to better match theri usage.Michal Krol
2009-07-15i965: the offset of any branch/jump instruction is in unit of 64bits on IGDNGXiang, Haihao
2009-07-13i965: add support for new chipsetsXiang, Haihao
2009-06-26i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger
2009-06-19i965: asst clean-ups, var renaming in brw_wm_emit_glsl()Brian Paul
2009-06-16i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger
2009-06-02i965: Support OPCODE_TRUNC in the brw_wm_fp.c code.Eric Anholt
2009-05-14i965: Fix register allocation of GLSL fp inputs.Eric Anholt
2009-05-12i965: enable additional code in emit_fb_write()Brian Paul
2009-05-11i965: handle extended swizzle terms (0,1) in get_src_reg()Brian Paul
2009-05-08i965: don't use GRF regs 126,127 for WM programsBrian Paul
2009-05-06i965: Remove bad constant buffer constant-reg-already-loaded optimization.Eric Anholt
2009-05-01Merge branch 'const-buffer-changes'Brian Paul
2009-04-27i965: only upload constant buffer data when we actually need the const bufferBrian Paul
2009-04-27i965: only upload constant buffer data when we actually need the const bufferBrian Paul
2009-04-24i965: rework GLSL/WM register allocationBrian Paul
2009-04-21i965: const correctnessBrian Paul